James M. Mitchell

Array ( [id] => 4985973 [patent_doc_number] => 20070152311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Chip-packaging compositions including bis-maleimides, packages made therewith, and methods of assembling same' [patent_app_type] => utility [patent_app_number] => 11/323475 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10151 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20070152311.pdf [firstpage_image] =>[orig_patent_app_number] => 11323475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5869072 [patent_doc_number] => 20060163689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Semiconductor device having reduced die-warpage and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/320985 [patent_app_country] => US [patent_app_date] => 2005-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6588 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20060163689.pdf [firstpage_image] =>[orig_patent_app_number] => 11320985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5019570 [patent_doc_number] => 20070145536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Compliant terminal mountings with vented spaces and methods' [patent_app_type] => utility [patent_app_number] => 11/318815 [patent_app_country] => US [patent_app_date] => 2005-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6429 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20070145536.pdf [firstpage_image] =>[orig_patent_app_number] => 11318815 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5645984 [patent_doc_number] => 20060131716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Stacking system and method' [patent_app_type] => utility [patent_app_number] => 11/317425 [patent_app_country] => US [patent_app_date] => 2005-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7222 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20060131716.pdf [firstpage_image] =>[orig_patent_app_number] => 11317425 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5805168 [patent_doc_number] => 20060091521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Stacking system and method' [patent_app_type] => utility [patent_app_number] => 11/316505 [patent_app_country] => US [patent_app_date] => 2005-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 7227 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20060091521.pdf [firstpage_image] =>[orig_patent_app_number] => 11316505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5593880 [patent_doc_number] => 20060157796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'Semiconductor device having dual gate electrode and related method of formation' [patent_app_type] => utility [patent_app_number] => 11/312806 [patent_app_country] => US [patent_app_date] => 2005-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6043 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20060157796.pdf [firstpage_image] =>[orig_patent_app_number] => 11312806 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5683030 [patent_doc_number] => 20060199300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-07 [patent_title] => 'IC chip solder bump structure and method of manufacturing same' [patent_app_type] => utility [patent_app_number] => 11/306015 [patent_app_country] => US [patent_app_date] => 2005-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20060199300.pdf [firstpage_image] =>[orig_patent_app_number] => 11306015 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5694257 [patent_doc_number] => 20060154404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Die paddle clamping method for wire bond enhancement' [patent_app_type] => utility [patent_app_number] => 11/301344 [patent_app_country] => US [patent_app_date] => 2005-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3130 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20060154404.pdf [firstpage_image] =>[orig_patent_app_number] => 11301344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7515859 [patent_doc_number] => 08039931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-18 [patent_title] => 'Power semiconductor component having a topmost metallization layer' [patent_app_type] => utility [patent_app_number] => 11/287736 [patent_app_country] => US [patent_app_date] => 2005-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5176 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/039/08039931.pdf [firstpage_image] =>[orig_patent_app_number] => 11287736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5645853 [patent_doc_number] => 20060131585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Thin film transistor array panel' [patent_app_type] => utility [patent_app_number] => 11/285935 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7172 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20060131585.pdf [firstpage_image] =>[orig_patent_app_number] => 11285935 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4487569 [patent_doc_number] => 07902639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Printable electric circuits, electronic components and method of forming the same' [patent_app_type] => utility [patent_app_number] => 11/280986 [patent_app_country] => US [patent_app_date] => 2005-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 18155 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/902/07902639.pdf [firstpage_image] =>[orig_patent_app_number] => 11280986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9099458 [patent_doc_number] => 08563331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Process for fabricating and repairing an electronic device' [patent_app_type] => utility [patent_app_number] => 11/270153 [patent_app_country] => US [patent_app_date] => 2005-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 20425 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11270153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 521226 [patent_doc_number] => 07186576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Stacked die module and techniques for forming a stacked die module' [patent_app_type] => utility [patent_app_number] => 11/266972 [patent_app_country] => US [patent_app_date] => 2005-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4956 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/186/07186576.pdf [firstpage_image] =>[orig_patent_app_number] => 11266972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5838294 [patent_doc_number] => 20060118952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Micro-hole plating method, gold bump fabrication method and semiconductor device fabrication method using the micro-hole plating method, semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/266095 [patent_app_country] => US [patent_app_date] => 2005-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9010 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20060118952.pdf [firstpage_image] =>[orig_patent_app_number] => 11266095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5040784 [patent_doc_number] => 20070093066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Stacked wafer or die packaging with enhanced thermal and device performance' [patent_app_type] => utility [patent_app_number] => 11/257595 [patent_app_country] => US [patent_app_date] => 2005-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5151 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20070093066.pdf [firstpage_image] =>[orig_patent_app_number] => 11257595 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5741312 [patent_doc_number] => 20060087034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-27 [patent_title] => 'Bumping process and structure thereof' [patent_app_type] => utility [patent_app_number] => 11/236196 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20060087034.pdf [firstpage_image] =>[orig_patent_app_number] => 11236196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9216763 [patent_doc_number] => 08629566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Semiconductor multichip module package with improved thermal performance; reduced size and improved moisture resistance' [patent_app_type] => utility [patent_app_number] => 11/235442 [patent_app_country] => US [patent_app_date] => 2005-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1159 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11235442 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5774078 [patent_doc_number] => 20060102990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Carrier for substrate film' [patent_app_type] => utility [patent_app_number] => 11/220191 [patent_app_country] => US [patent_app_date] => 2005-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20060102990.pdf [firstpage_image] =>[orig_patent_app_number] => 11220191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5800552 [patent_doc_number] => 20060035408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Methods for designing spacers for use in stacking semiconductor devices or semiconductor device components' [patent_app_type] => utility [patent_app_number] => 11/216600 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6406 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20060035408.pdf [firstpage_image] =>[orig_patent_app_number] => 11216600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 307338 [patent_doc_number] => 07531404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer' [patent_app_type] => utility [patent_app_number] => 11/216596 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3421 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/531/07531404.pdf [firstpage_image] =>[orig_patent_app_number] => 11216596 [rel_patent_id] =>[rel_patent_doc_number] =>)