Search

James M. Mitchell

Supervisory Patent Examiner (ID: 10382, Phone: (571)272-1931 , Office: P/4100 )

Most Active Art Unit
2813
Art Unit(s)
2813, 2827, 4100, 2822, 4127
Total Applications
769
Issued Applications
540
Pending Applications
13
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9153502 [patent_doc_number] => 08586408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Contact and method of formation' [patent_app_type] => utility [patent_app_number] => 13/291882 [patent_app_country] => US [patent_app_date] => 2011-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6314 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13291882 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/291882
Contact and method of formation Nov 7, 2011 Issued
Array ( [id] => 8193074 [patent_doc_number] => 20120119376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'SEMICONDUCTOR CHIPS AND METHODS OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/289624 [patent_app_country] => US [patent_app_date] => 2011-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10235 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20120119376.pdf [firstpage_image] =>[orig_patent_app_number] => 13289624 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/289624
SEMICONDUCTOR CHIPS AND METHODS OF FORMING THE SAME Nov 3, 2011 Abandoned
Array ( [id] => 8812039 [patent_doc_number] => 20130113084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-09 [patent_title] => 'SEMICONDUCTOR SUBSTRATE WITH MOLDED SUPPORT LAYER' [patent_app_type] => utility [patent_app_number] => 13/289761 [patent_app_country] => US [patent_app_date] => 2011-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4268 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13289761 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/289761
SEMICONDUCTOR SUBSTRATE WITH MOLDED SUPPORT LAYER Nov 3, 2011 Abandoned
Array ( [id] => 8730195 [patent_doc_number] => 20130075764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'OPTICAL MODULE PACKAGE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/288747 [patent_app_country] => US [patent_app_date] => 2011-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1122 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13288747 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/288747
OPTICAL MODULE PACKAGE STRUCTURE Nov 2, 2011 Abandoned
Array ( [id] => 9227403 [patent_doc_number] => 08633071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-21 [patent_title] => 'Silicon device on Si: C-oi and Sgoi and method of manufacture' [patent_app_type] => utility [patent_app_number] => 13/278667 [patent_app_country] => US [patent_app_date] => 2011-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4632 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13278667 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/278667
Silicon device on Si: C-oi and Sgoi and method of manufacture Oct 20, 2011 Issued
Array ( [id] => 9376307 [patent_doc_number] => 08680572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'Microdisplay packaging system' [patent_app_type] => utility [patent_app_number] => 13/273011 [patent_app_country] => US [patent_app_date] => 2011-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4088 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13273011 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/273011
Microdisplay packaging system Oct 12, 2011 Issued
Array ( [id] => 9608154 [patent_doc_number] => 08785321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-22 [patent_title] => 'Low resistance and reliable copper interconnects by variable doping' [patent_app_type] => utility [patent_app_number] => 13/249823 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2334 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13249823 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/249823
Low resistance and reliable copper interconnects by variable doping Sep 29, 2011 Issued
Array ( [id] => 7815223 [patent_doc_number] => 20120061843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/228591 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20120061843.pdf [firstpage_image] =>[orig_patent_app_number] => 13228591 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/228591
Semiconductor package and method for manufacturing the same Sep 8, 2011 Issued
Array ( [id] => 9455860 [patent_doc_number] => 08716874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Semiconductor device having metal posts non-overlapping with other devices and layout method of semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/228583 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4339 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13228583 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/228583
Semiconductor device having metal posts non-overlapping with other devices and layout method of semiconductor device Sep 8, 2011 Issued
Array ( [id] => 9239121 [patent_doc_number] => 08603912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'Power semiconductor component and method for the production thereof' [patent_app_type] => utility [patent_app_number] => 13/225675 [patent_app_country] => US [patent_app_date] => 2011-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5194 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13225675 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/225675
Power semiconductor component and method for the production thereof Sep 5, 2011 Issued
Array ( [id] => 7666822 [patent_doc_number] => 20110316091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'Semiconductor Devices, Assemblies And Constructions' [patent_app_type] => utility [patent_app_number] => 13/224804 [patent_app_country] => US [patent_app_date] => 2011-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 5695 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13224804 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/224804
Semiconductor devices, assemblies and constructions Sep 1, 2011 Issued
Array ( [id] => 9876037 [patent_doc_number] => 08963310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Low cost hybrid high density package' [patent_app_type] => utility [patent_app_number] => 13/216918 [patent_app_country] => US [patent_app_date] => 2011-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 5933 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13216918 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/216918
Low cost hybrid high density package Aug 23, 2011 Issued
Array ( [id] => 8680912 [patent_doc_number] => 20130049196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'THROUGH INTERPOSER WIRE BOND USING LOW CTE INTERPOSER WITH COARSE SLOT APERTURES' [patent_app_type] => utility [patent_app_number] => 13/216465 [patent_app_country] => US [patent_app_date] => 2011-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5705 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13216465 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/216465
Through interposer wire bond using low CTE interposer with coarse slot apertures Aug 23, 2011 Issued
Array ( [id] => 9112917 [patent_doc_number] => 08569086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Semiconductor device and method of dicing semiconductor devices' [patent_app_type] => utility [patent_app_number] => 13/216825 [patent_app_country] => US [patent_app_date] => 2011-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3572 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13216825 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/216825
Semiconductor device and method of dicing semiconductor devices Aug 23, 2011 Issued
Array ( [id] => 7787834 [patent_doc_number] => 20120049390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'ELECTRICAL COMPONENT AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/215457 [patent_app_country] => US [patent_app_date] => 2011-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5609 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20120049390.pdf [firstpage_image] =>[orig_patent_app_number] => 13215457 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/215457
Electrical component and method of manufacturing the same Aug 22, 2011 Issued
Array ( [id] => 8921509 [patent_doc_number] => 08487449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Carbon nanotube interconnection and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 13/215463 [patent_app_country] => US [patent_app_date] => 2011-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 37 [patent_no_of_words] => 8849 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13215463 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/215463
Carbon nanotube interconnection and manufacturing method thereof Aug 22, 2011 Issued
Array ( [id] => 7805357 [patent_doc_number] => 20120056309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-08 [patent_title] => 'SEMICONDUCTOR DEVICE WITH REDUCED HEAT-INDUCED LOSS' [patent_app_type] => utility [patent_app_number] => 13/215419 [patent_app_country] => US [patent_app_date] => 2011-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3782 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20120056309.pdf [firstpage_image] =>[orig_patent_app_number] => 13215419 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/215419
SEMICONDUCTOR DEVICE WITH REDUCED HEAT-INDUCED LOSS Aug 22, 2011 Abandoned
Array ( [id] => 8680948 [patent_doc_number] => 20130049232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'COMPONENT ASSEMBLY USING A TEMPORARY ATTACH MATERIAL' [patent_app_type] => utility [patent_app_number] => 13/215393 [patent_app_country] => US [patent_app_date] => 2011-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3990 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13215393 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/215393
Component assembly using a temporary attach material Aug 22, 2011 Issued
Array ( [id] => 8680920 [patent_doc_number] => 20130049204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING DIFFUSION SOLDERED LAYER ON SINTERED SILVER LAYER' [patent_app_type] => utility [patent_app_number] => 13/214379 [patent_app_country] => US [patent_app_date] => 2011-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4026 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13214379 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/214379
Semiconductor device including diffusion soldered layer on sintered silver layer Aug 21, 2011 Issued
Array ( [id] => 8669432 [patent_doc_number] => 20130043970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'METHOD AND APPARATUS FOR ACHIEVING GALVANIC ISOLATION IN PACKAGE HAVING INTEGRAL ISOLATION MEDIUM' [patent_app_type] => utility [patent_app_number] => 13/214069 [patent_app_country] => US [patent_app_date] => 2011-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8951 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13214069 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/214069
Method and apparatus for achieving galvanic isolation in package having integral isolation medium Aug 18, 2011 Issued
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