Search

James M. Mitchell

Supervisory Patent Examiner (ID: 19356, Phone: (571)272-1931 , Office: P/4100 )

Most Active Art Unit
2813
Art Unit(s)
4100, 2827, 2822, 2813, 4127
Total Applications
769
Issued Applications
540
Pending Applications
13
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5874617 [patent_doc_number] => 20060166497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'METHOD OF FABRICATING CONDUCTIVE LINES' [patent_app_type] => utility [patent_app_number] => 11/162115 [patent_app_country] => US [patent_app_date] => 2005-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3619 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20060166497.pdf [firstpage_image] =>[orig_patent_app_number] => 11162115 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/162115
Method of fabricating conductive lines with silicide layer Aug 28, 2005 Issued
Array ( [id] => 6929070 [patent_doc_number] => 20050280103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Strained-semiconductor-on-insulator finFET device structures' [patent_app_type] => utility [patent_app_number] => 11/211933 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 15394 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20050280103.pdf [firstpage_image] =>[orig_patent_app_number] => 11211933 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/211933
Strained-semiconductor-on-insulator finFET device structures Aug 24, 2005 Issued
Array ( [id] => 5590962 [patent_doc_number] => 20060040414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Methods of forming conductive materials' [patent_app_type] => utility [patent_app_number] => 11/209080 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2234 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20060040414.pdf [firstpage_image] =>[orig_patent_app_number] => 11209080 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/209080
Methods of forming conductive materials Aug 21, 2005 Abandoned
Array ( [id] => 6975447 [patent_doc_number] => 20050285162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Semiconductor devices having a stacked structure and methods of forming the same' [patent_app_type] => utility [patent_app_number] => 11/159596 [patent_app_country] => US [patent_app_date] => 2005-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7597 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20050285162.pdf [firstpage_image] =>[orig_patent_app_number] => 11159596 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/159596
Semiconductor devices having a stacked structure and methods of forming the same Jun 22, 2005 Abandoned
Array ( [id] => 5602362 [patent_doc_number] => 20060292707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Healing detrimental bonds in deposited materials' [patent_app_type] => utility [patent_app_number] => 11/159506 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6236 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20060292707.pdf [firstpage_image] =>[orig_patent_app_number] => 11159506 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/159506
Healing detrimental bonds in deposited materials Jun 21, 2005 Issued
Array ( [id] => 6931324 [patent_doc_number] => 20050282359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Wafer processing method' [patent_app_type] => utility [patent_app_number] => 11/151526 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7142 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20050282359.pdf [firstpage_image] =>[orig_patent_app_number] => 11151526 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/151526
Wafer processing method including formation of a deteriorated layer Jun 13, 2005 Issued
Array ( [id] => 876161 [patent_doc_number] => 07358170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'Methods of forming conductive interconnects, and methods of depositing nickel' [patent_app_type] => utility [patent_app_number] => 11/149578 [patent_app_country] => US [patent_app_date] => 2005-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3340 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/358/07358170.pdf [firstpage_image] =>[orig_patent_app_number] => 11149578 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/149578
Methods of forming conductive interconnects, and methods of depositing nickel Jun 8, 2005 Issued
Array ( [id] => 319012 [patent_doc_number] => 07521724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-21 [patent_title] => 'Light emitting diode package and process of making the same' [patent_app_type] => utility [patent_app_number] => 11/147185 [patent_app_country] => US [patent_app_date] => 2005-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 2894 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/521/07521724.pdf [firstpage_image] =>[orig_patent_app_number] => 11147185 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/147185
Light emitting diode package and process of making the same Jun 7, 2005 Issued
Array ( [id] => 7056095 [patent_doc_number] => 20050277270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Wafer processing method' [patent_app_type] => utility [patent_app_number] => 11/147245 [patent_app_country] => US [patent_app_date] => 2005-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8401 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20050277270.pdf [firstpage_image] =>[orig_patent_app_number] => 11147245 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/147245
Wafer processing method Jun 7, 2005 Issued
Array ( [id] => 496976 [patent_doc_number] => 07208402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Method and apparatus for improved power routing' [patent_app_type] => utility [patent_app_number] => 11/144974 [patent_app_country] => US [patent_app_date] => 2005-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3240 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/208/07208402.pdf [firstpage_image] =>[orig_patent_app_number] => 11144974 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/144974
Method and apparatus for improved power routing Jun 2, 2005 Issued
Array ( [id] => 6977987 [patent_doc_number] => 20050287705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Flip chip on leadframe package and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/138406 [patent_app_country] => US [patent_app_date] => 2005-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2628 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0287/20050287705.pdf [firstpage_image] =>[orig_patent_app_number] => 11138406 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/138406
Flip chip on leadframe package and method for manufacturing the same May 26, 2005 Abandoned
Array ( [id] => 7019514 [patent_doc_number] => 20050221533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-06 [patent_title] => 'Method of making chip package with grease heat sink' [patent_app_type] => utility [patent_app_number] => 11/137026 [patent_app_country] => US [patent_app_date] => 2005-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4581 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20050221533.pdf [firstpage_image] =>[orig_patent_app_number] => 11137026 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/137026
Method of making chip package with grease heat sink May 24, 2005 Abandoned
Array ( [id] => 6958607 [patent_doc_number] => 20050214977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Microelectronic packaging and methods for thermally protecting package interconnects and components' [patent_app_type] => utility [patent_app_number] => 11/135776 [patent_app_country] => US [patent_app_date] => 2005-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6114 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20050214977.pdf [firstpage_image] =>[orig_patent_app_number] => 11135776 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/135776
Microelectronic packaging and methods for thermally protecting package interconnects and components May 22, 2005 Abandoned
Array ( [id] => 7111335 [patent_doc_number] => 20050208791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'System and apparatus for socket and package power/ground bar to increase current carrying capacity for higher IC power delivery' [patent_app_type] => utility [patent_app_number] => 11/133999 [patent_app_country] => US [patent_app_date] => 2005-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3269 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20050208791.pdf [firstpage_image] =>[orig_patent_app_number] => 11133999 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/133999
System and apparatus for socket and package power/ground bar to increase current carrying capacity for higher IC power delivery May 19, 2005 Issued
Array ( [id] => 836955 [patent_doc_number] => 07393770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Backside method for fabricating semiconductor components with conductive interconnects' [patent_app_type] => utility [patent_app_number] => 11/133085 [patent_app_country] => US [patent_app_date] => 2005-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 61 [patent_no_of_words] => 12398 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/393/07393770.pdf [firstpage_image] =>[orig_patent_app_number] => 11133085 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/133085
Backside method for fabricating semiconductor components with conductive interconnects May 18, 2005 Issued
Array ( [id] => 5622852 [patent_doc_number] => 20060261357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'Array-type modularized light-emitting diode structure and a method for packaging the structure' [patent_app_type] => utility [patent_app_number] => 11/131395 [patent_app_country] => US [patent_app_date] => 2005-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4309 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20060261357.pdf [firstpage_image] =>[orig_patent_app_number] => 11131395 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/131395
Array-type modularized light-emitting diode structure and a method for packaging the structure May 17, 2005 Issued
Array ( [id] => 5732934 [patent_doc_number] => 20060258051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Method and system for solder die attach' [patent_app_type] => utility [patent_app_number] => 11/126016 [patent_app_country] => US [patent_app_date] => 2005-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1787 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0258/20060258051.pdf [firstpage_image] =>[orig_patent_app_number] => 11126016 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/126016
Method and system for solder die attach May 9, 2005 Abandoned
Array ( [id] => 43763 [patent_doc_number] => 07776736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Substrate for electronic device capable of suppressing fluorine atoms exposed at the surface of insulating film from reacting with water and method for processing same' [patent_app_type] => utility [patent_app_number] => 11/596186 [patent_app_country] => US [patent_app_date] => 2005-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8676 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/776/07776736.pdf [firstpage_image] =>[orig_patent_app_number] => 11596186 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/596186
Substrate for electronic device capable of suppressing fluorine atoms exposed at the surface of insulating film from reacting with water and method for processing same May 9, 2005 Issued
Array ( [id] => 7045652 [patent_doc_number] => 20050250247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Method for internal electrical insulation of a substrate for a power semiconductor module' [patent_app_type] => utility [patent_app_number] => 11/122175 [patent_app_country] => US [patent_app_date] => 2005-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1940 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20050250247.pdf [firstpage_image] =>[orig_patent_app_number] => 11122175 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/122175
Method for internal electrical insulation of a substrate for a power semiconductor module May 3, 2005 Issued
Array ( [id] => 7176676 [patent_doc_number] => 20050189623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-01 [patent_title] => 'Multiple die package' [patent_app_type] => utility [patent_app_number] => 11/120941 [patent_app_country] => US [patent_app_date] => 2005-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20050189623.pdf [firstpage_image] =>[orig_patent_app_number] => 11120941 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/120941
Multiple die package May 2, 2005 Abandoned
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