Search

James M. Mitchell

Supervisory Patent Examiner (ID: 19356, Phone: (571)272-1931 , Office: P/4100 )

Most Active Art Unit
2813
Art Unit(s)
4100, 2827, 2822, 2813, 4127
Total Applications
769
Issued Applications
540
Pending Applications
13
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5834784 [patent_doc_number] => 20060246615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Method of manufacturing vertical cavity surface emitting laser' [patent_app_type] => utility [patent_app_number] => 11/115285 [patent_app_country] => US [patent_app_date] => 2005-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1679 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20060246615.pdf [firstpage_image] =>[orig_patent_app_number] => 11115285 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/115285
Method of manufacturing vertical cavity surface emitting laser Apr 26, 2005 Abandoned
Array ( [id] => 5631757 [patent_doc_number] => 20060148227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Method for fabricating a first contact hole plane in a memory module' [patent_app_type] => utility [patent_app_number] => 11/115385 [patent_app_country] => US [patent_app_date] => 2005-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5292 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20060148227.pdf [firstpage_image] =>[orig_patent_app_number] => 11115385 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/115385
Method for fabricating a first contact hole plane in a memory module Apr 26, 2005 Abandoned
Array ( [id] => 5854616 [patent_doc_number] => 20060226549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Semiconductor device and fabricating method thereof' [patent_app_type] => utility [patent_app_number] => 11/104266 [patent_app_country] => US [patent_app_date] => 2005-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20060226549.pdf [firstpage_image] =>[orig_patent_app_number] => 11104266 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/104266
Semiconductor device and fabricating method thereof Apr 11, 2005 Abandoned
Array ( [id] => 5765835 [patent_doc_number] => 20050263848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Metal-insulator-metal capacitor having a large capacitance and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/097165 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4176 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20050263848.pdf [firstpage_image] =>[orig_patent_app_number] => 11097165 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/097165
Metal-insulator-metal capacitor having a large capacitance and method of manufacturing the same Apr 3, 2005 Abandoned
Array ( [id] => 7133010 [patent_doc_number] => 20050179141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-18 [patent_title] => 'Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer' [patent_app_type] => utility [patent_app_number] => 11/095006 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5080 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20050179141.pdf [firstpage_image] =>[orig_patent_app_number] => 11095006 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/095006
Methods of forming metal interconnections of semiconductor devices by treating a barrier metal layer Mar 30, 2005 Issued
Array ( [id] => 7048471 [patent_doc_number] => 20050184358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'High performance system-on-chip using post passivation process' [patent_app_type] => utility [patent_app_number] => 11/092379 [patent_app_country] => US [patent_app_date] => 2005-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8632 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20050184358.pdf [firstpage_image] =>[orig_patent_app_number] => 11092379 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/092379
High performance system-on-chip using post passivation process Mar 28, 2005 Issued
Array ( [id] => 584748 [patent_doc_number] => 07442573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Scaffold-organized clusters and electronic devices made using such clusters' [patent_app_type] => utility [patent_app_number] => 11/094049 [patent_app_country] => US [patent_app_date] => 2005-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 18433 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/442/07442573.pdf [firstpage_image] =>[orig_patent_app_number] => 11094049 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/094049
Scaffold-organized clusters and electronic devices made using such clusters Mar 28, 2005 Issued
Array ( [id] => 881092 [patent_doc_number] => 07355231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Memory circuitry with oxygen diffusion barrier layer received over a well base' [patent_app_type] => utility [patent_app_number] => 11/091260 [patent_app_country] => US [patent_app_date] => 2005-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 2732 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/355/07355231.pdf [firstpage_image] =>[orig_patent_app_number] => 11091260 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/091260
Memory circuitry with oxygen diffusion barrier layer received over a well base Mar 27, 2005 Issued
Array ( [id] => 5697597 [patent_doc_number] => 20060214281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Stress absorption layer and cylinder solder joint method and apparatus' [patent_app_type] => utility [patent_app_number] => 11/089995 [patent_app_country] => US [patent_app_date] => 2005-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2550 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20060214281.pdf [firstpage_image] =>[orig_patent_app_number] => 11089995 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/089995
Stress absorption layer and cylinder solder joint method and apparatus Mar 24, 2005 Issued
Array ( [id] => 5760287 [patent_doc_number] => 20060211232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Method for Manufacturing Gold Bumps' [patent_app_type] => utility [patent_app_number] => 10/907005 [patent_app_country] => US [patent_app_date] => 2005-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2059 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20060211232.pdf [firstpage_image] =>[orig_patent_app_number] => 10907005 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/907005
Method for Manufacturing Gold Bumps Mar 15, 2005 Abandoned
Array ( [id] => 5596356 [patent_doc_number] => 20060160273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'METHOD FOR WAFER LEVEL PACKAGING' [patent_app_type] => utility [patent_app_number] => 10/906935 [patent_app_country] => US [patent_app_date] => 2005-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20060160273.pdf [firstpage_image] =>[orig_patent_app_number] => 10906935 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/906935
METHOD FOR WAFER LEVEL PACKAGING Mar 13, 2005 Abandoned
Array ( [id] => 307339 [patent_doc_number] => 07531405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Method of manufacturing a dielectric layer and corresponding semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/067496 [patent_app_country] => US [patent_app_date] => 2005-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2125 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/531/07531405.pdf [firstpage_image] =>[orig_patent_app_number] => 11067496 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/067496
Method of manufacturing a dielectric layer and corresponding semiconductor device Feb 27, 2005 Issued
Array ( [id] => 7236923 [patent_doc_number] => 20050140030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Scribe street width reduction by deep trench and shallow saw cut' [patent_app_type] => utility [patent_app_number] => 11/066380 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3780 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140030.pdf [firstpage_image] =>[orig_patent_app_number] => 11066380 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/066380
Scribe street width reduction by deep trench and shallow saw cut Feb 24, 2005 Abandoned
Array ( [id] => 7050907 [patent_doc_number] => 20050186794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/061625 [patent_app_country] => US [patent_app_date] => 2005-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5819 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20050186794.pdf [firstpage_image] =>[orig_patent_app_number] => 11061625 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/061625
Method for fabricating semiconductor device Feb 21, 2005 Issued
Array ( [id] => 5675524 [patent_doc_number] => 20060180879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Method to enhance the initiation of film growth' [patent_app_type] => utility [patent_app_number] => 11/060105 [patent_app_country] => US [patent_app_date] => 2005-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5648 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20060180879.pdf [firstpage_image] =>[orig_patent_app_number] => 11060105 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/060105
Method to enhance the initiation of film growth Feb 15, 2005 Issued
Array ( [id] => 6955767 [patent_doc_number] => 20050212137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Semiconductor device having a multilayer interconnection structure and fabrication method\nthereof' [patent_app_type] => utility [patent_app_number] => 11/042355 [patent_app_country] => US [patent_app_date] => 2005-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6874 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20050212137.pdf [firstpage_image] =>[orig_patent_app_number] => 11042355 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/042355
Semiconductor device having a multilayer interconnection structure and fabrication method thereof Jan 25, 2005 Issued
Array ( [id] => 5874590 [patent_doc_number] => 20060166484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Method for Cu metallization of highly reliable dual damascene structures' [patent_app_type] => utility [patent_app_number] => 11/040366 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20060166484.pdf [firstpage_image] =>[orig_patent_app_number] => 11040366 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/040366
Method for Cu metallization of highly reliable dual damascene structures Jan 20, 2005 Issued
Array ( [id] => 5869114 [patent_doc_number] => 20060163731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Dual damascene interconnections employing a copper alloy at the copper/barrier interface' [patent_app_type] => utility [patent_app_number] => 11/040865 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2366 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20060163731.pdf [firstpage_image] =>[orig_patent_app_number] => 11040865 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/040865
Dual damascene interconnections employing a copper alloy at the copper/barrier interface Jan 20, 2005 Abandoned
Array ( [id] => 5869114 [patent_doc_number] => 20060163731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Dual damascene interconnections employing a copper alloy at the copper/barrier interface' [patent_app_type] => utility [patent_app_number] => 11/040865 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2366 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20060163731.pdf [firstpage_image] =>[orig_patent_app_number] => 11040865 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/040865
Dual damascene interconnections employing a copper alloy at the copper/barrier interface Jan 20, 2005 Abandoned
Array ( [id] => 5874590 [patent_doc_number] => 20060166484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Method for Cu metallization of highly reliable dual damascene structures' [patent_app_type] => utility [patent_app_number] => 11/040366 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20060166484.pdf [firstpage_image] =>[orig_patent_app_number] => 11040366 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/040366
Method for Cu metallization of highly reliable dual damascene structures Jan 20, 2005 Issued
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