Search

James M. Mitchell

Supervisory Patent Examiner (ID: 19356, Phone: (571)272-1931 , Office: P/4100 )

Most Active Art Unit
2813
Art Unit(s)
4100, 2827, 2822, 2813, 4127
Total Applications
769
Issued Applications
540
Pending Applications
13
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 840827 [patent_doc_number] => 07391119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-24 [patent_title] => 'Temperature sustaining flip chip assembly process' [patent_app_type] => utility [patent_app_number] => 11/040345 [patent_app_country] => US [patent_app_date] => 2005-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3356 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/391/07391119.pdf [firstpage_image] =>[orig_patent_app_number] => 11040345 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/040345
Temperature sustaining flip chip assembly process Jan 19, 2005 Issued
Array ( [id] => 7036852 [patent_doc_number] => 20050156286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Method for improving a physical property defect value of a gate dielectric' [patent_app_type] => utility [patent_app_number] => 11/038545 [patent_app_country] => US [patent_app_date] => 2005-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4369 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20050156286.pdf [firstpage_image] =>[orig_patent_app_number] => 11038545 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/038545
Method for improving a physical property defect value of a gate dielectric Jan 17, 2005 Abandoned
Array ( [id] => 7036890 [patent_doc_number] => 20050156324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Method for manufacturing connection construction' [patent_app_type] => utility [patent_app_number] => 11/036135 [patent_app_country] => US [patent_app_date] => 2005-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5678 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20050156324.pdf [firstpage_image] =>[orig_patent_app_number] => 11036135 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/036135
Method for manufacturing connection construction Jan 17, 2005 Abandoned
Array ( [id] => 6980797 [patent_doc_number] => 20050150865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Pattern film forming method and pattern film forming apparatus' [patent_app_type] => utility [patent_app_number] => 11/034805 [patent_app_country] => US [patent_app_date] => 2005-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 12493 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20050150865.pdf [firstpage_image] =>[orig_patent_app_number] => 11034805 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/034805
Pattern film forming method and pattern film forming apparatus Jan 13, 2005 Issued
Array ( [id] => 121599 [patent_doc_number] => 07709383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-04 [patent_title] => 'Film forming method, and substrate-processing apparatus' [patent_app_type] => utility [patent_app_number] => 11/034926 [patent_app_country] => US [patent_app_date] => 2005-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 8628 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/709/07709383.pdf [firstpage_image] =>[orig_patent_app_number] => 11034926 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/034926
Film forming method, and substrate-processing apparatus Jan 13, 2005 Issued
Array ( [id] => 4539432 [patent_doc_number] => 07875547 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Contact hole structures and contact structures and fabrication methods thereof' [patent_app_type] => utility [patent_app_number] => 11/035325 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5603 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/875/07875547.pdf [firstpage_image] =>[orig_patent_app_number] => 11035325 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/035325
Contact hole structures and contact structures and fabrication methods thereof Jan 11, 2005 Issued
Array ( [id] => 7169052 [patent_doc_number] => 20050121711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Chip and wafer integration process using vertical connections' [patent_app_type] => utility [patent_app_number] => 11/033926 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 3530 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20050121711.pdf [firstpage_image] =>[orig_patent_app_number] => 11033926 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/033926
Chip and wafer integration process using vertical connections Jan 11, 2005 Issued
Array ( [id] => 826848 [patent_doc_number] => 07402513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Method for forming interlayer insulation film' [patent_app_type] => utility [patent_app_number] => 11/034616 [patent_app_country] => US [patent_app_date] => 2005-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4376 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/402/07402513.pdf [firstpage_image] =>[orig_patent_app_number] => 11034616 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/034616
Method for forming interlayer insulation film Jan 11, 2005 Issued
Array ( [id] => 579367 [patent_doc_number] => 07452802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Method of forming metal wiring for high voltage element' [patent_app_type] => utility [patent_app_number] => 11/030786 [patent_app_country] => US [patent_app_date] => 2005-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2661 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/452/07452802.pdf [firstpage_image] =>[orig_patent_app_number] => 11030786 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/030786
Method of forming metal wiring for high voltage element Jan 6, 2005 Issued
Array ( [id] => 7036892 [patent_doc_number] => 20050156326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Board for mounting BGA semiconductor chip thereon, semiconductor device, and methods of fabricating such board and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/029676 [patent_app_country] => US [patent_app_date] => 2005-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9245 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20050156326.pdf [firstpage_image] =>[orig_patent_app_number] => 11029676 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/029676
Board for mounting BGA semiconductor chip thereon, semiconductor device, and methods of fabricating such board and semiconductor device Jan 5, 2005 Issued
Array ( [id] => 7169289 [patent_doc_number] => 20050121803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Internally reinforced bond pads' [patent_app_type] => utility [patent_app_number] => 11/030496 [patent_app_country] => US [patent_app_date] => 2005-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2683 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20050121803.pdf [firstpage_image] =>[orig_patent_app_number] => 11030496 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/030496
Internally reinforced bond pads Jan 5, 2005 Issued
Array ( [id] => 7253763 [patent_doc_number] => 20050142844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Method for fabricating metal interconnect in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/026916 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1423 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142844.pdf [firstpage_image] =>[orig_patent_app_number] => 11026916 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/026916
Method for fabricating metal interconnect in semiconductor device Dec 29, 2004 Abandoned
Array ( [id] => 7253840 [patent_doc_number] => 20050142865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Methods of fabricating via hole and trench' [patent_app_type] => utility [patent_app_number] => 11/027435 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1640 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142865.pdf [firstpage_image] =>[orig_patent_app_number] => 11027435 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/027435
Methods of fabricating via hole and trench Dec 29, 2004 Issued
Array ( [id] => 386619 [patent_doc_number] => 07303988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Methods of manufacturing multi-level metal lines in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/027035 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2184 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/303/07303988.pdf [firstpage_image] =>[orig_patent_app_number] => 11027035 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/027035
Methods of manufacturing multi-level metal lines in semiconductor devices Dec 29, 2004 Issued
Array ( [id] => 512396 [patent_doc_number] => 07199440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'Techniques for joining an opto-electronic module to a semiconductor package' [patent_app_type] => utility [patent_app_number] => 11/026749 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 5313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/199/07199440.pdf [firstpage_image] =>[orig_patent_app_number] => 11026749 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/026749
Techniques for joining an opto-electronic module to a semiconductor package Dec 29, 2004 Issued
Array ( [id] => 7253761 [patent_doc_number] => 20050142843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Method for forming metallic interconnects in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 11/026756 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1371 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20050142843.pdf [firstpage_image] =>[orig_patent_app_number] => 11026756 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/026756
Method for forming metallic interconnects in semiconductor devices Dec 29, 2004 Issued
Array ( [id] => 860212 [patent_doc_number] => 07371606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'Manufacturing method of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/012156 [patent_app_country] => US [patent_app_date] => 2004-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 46 [patent_no_of_words] => 14604 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/371/07371606.pdf [firstpage_image] =>[orig_patent_app_number] => 11012156 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/012156
Manufacturing method of a semiconductor device Dec 15, 2004 Issued
Array ( [id] => 359610 [patent_doc_number] => 07485489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Electronics circuit manufacture' [patent_app_type] => utility [patent_app_number] => 11/012196 [patent_app_country] => US [patent_app_date] => 2004-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5399 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/485/07485489.pdf [firstpage_image] =>[orig_patent_app_number] => 11012196 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/012196
Electronics circuit manufacture Dec 15, 2004 Issued
Array ( [id] => 6915510 [patent_doc_number] => 20050093071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Substrate based ESD network protection for a flip chip' [patent_app_type] => utility [patent_app_number] => 11/009450 [patent_app_country] => US [patent_app_date] => 2004-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3796 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093071.pdf [firstpage_image] =>[orig_patent_app_number] => 11009450 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/009450
Substrate based ESD network protection for a flip chip Dec 9, 2004 Issued
Array ( [id] => 442866 [patent_doc_number] => 07256126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-08-14 [patent_title] => 'Pitch reduction integrating formation of memory array and peripheral circuitry' [patent_app_type] => utility [patent_app_number] => 11/009496 [patent_app_country] => US [patent_app_date] => 2004-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 5006 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/256/07256126.pdf [firstpage_image] =>[orig_patent_app_number] => 11009496 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/009496
Pitch reduction integrating formation of memory array and peripheral circuitry Dec 9, 2004 Issued
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