
James M. Mitchell
Supervisory Patent Examiner (ID: 19356, Phone: (571)272-1931 , Office: P/4100 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 4100, 2827, 2822, 2813, 4127 |
| Total Applications | 769 |
| Issued Applications | 540 |
| Pending Applications | 13 |
| Abandoned Applications | 218 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 840827
[patent_doc_number] => 07391119
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-06-24
[patent_title] => 'Temperature sustaining flip chip assembly process'
[patent_app_type] => utility
[patent_app_number] => 11/040345
[patent_app_country] => US
[patent_app_date] => 2005-01-20
[patent_effective_date] => 0000-00-00
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[patent_figures_cnt] => 5
[patent_no_of_words] => 3356
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/391/07391119.pdf
[firstpage_image] =>[orig_patent_app_number] => 11040345
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/040345 | Temperature sustaining flip chip assembly process | Jan 19, 2005 | Issued |
Array
(
[id] => 7036852
[patent_doc_number] => 20050156286
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'Method for improving a physical property defect value of a gate dielectric'
[patent_app_type] => utility
[patent_app_number] => 11/038545
[patent_app_country] => US
[patent_app_date] => 2005-01-18
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 11038545
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/038545 | Method for improving a physical property defect value of a gate dielectric | Jan 17, 2005 | Abandoned |
Array
(
[id] => 7036890
[patent_doc_number] => 20050156324
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'Method for manufacturing connection construction'
[patent_app_type] => utility
[patent_app_number] => 11/036135
[patent_app_country] => US
[patent_app_date] => 2005-01-18
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[firstpage_image] =>[orig_patent_app_number] => 11036135
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/036135 | Method for manufacturing connection construction | Jan 17, 2005 | Abandoned |
Array
(
[id] => 6980797
[patent_doc_number] => 20050150865
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-14
[patent_title] => 'Pattern film forming method and pattern film forming apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/034805
[patent_app_country] => US
[patent_app_date] => 2005-01-14
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[firstpage_image] =>[orig_patent_app_number] => 11034805
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/034805 | Pattern film forming method and pattern film forming apparatus | Jan 13, 2005 | Issued |
Array
(
[id] => 121599
[patent_doc_number] => 07709383
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-04
[patent_title] => 'Film forming method, and substrate-processing apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/034926
[patent_app_country] => US
[patent_app_date] => 2005-01-14
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[firstpage_image] =>[orig_patent_app_number] => 11034926
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/034926 | Film forming method, and substrate-processing apparatus | Jan 13, 2005 | Issued |
Array
(
[id] => 4539432
[patent_doc_number] => 07875547
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-25
[patent_title] => 'Contact hole structures and contact structures and fabrication methods thereof'
[patent_app_type] => utility
[patent_app_number] => 11/035325
[patent_app_country] => US
[patent_app_date] => 2005-01-12
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[pdf_file] => patents/07/875/07875547.pdf
[firstpage_image] =>[orig_patent_app_number] => 11035325
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/035325 | Contact hole structures and contact structures and fabrication methods thereof | Jan 11, 2005 | Issued |
Array
(
[id] => 7169052
[patent_doc_number] => 20050121711
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Chip and wafer integration process using vertical connections'
[patent_app_type] => utility
[patent_app_number] => 11/033926
[patent_app_country] => US
[patent_app_date] => 2005-01-12
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[pdf_file] => publications/A1/0121/20050121711.pdf
[firstpage_image] =>[orig_patent_app_number] => 11033926
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/033926 | Chip and wafer integration process using vertical connections | Jan 11, 2005 | Issued |
Array
(
[id] => 826848
[patent_doc_number] => 07402513
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-22
[patent_title] => 'Method for forming interlayer insulation film'
[patent_app_type] => utility
[patent_app_number] => 11/034616
[patent_app_country] => US
[patent_app_date] => 2005-01-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/402/07402513.pdf
[firstpage_image] =>[orig_patent_app_number] => 11034616
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/034616 | Method for forming interlayer insulation film | Jan 11, 2005 | Issued |
Array
(
[id] => 579367
[patent_doc_number] => 07452802
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-11-18
[patent_title] => 'Method of forming metal wiring for high voltage element'
[patent_app_type] => utility
[patent_app_number] => 11/030786
[patent_app_country] => US
[patent_app_date] => 2005-01-07
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[pdf_file] => patents/07/452/07452802.pdf
[firstpage_image] =>[orig_patent_app_number] => 11030786
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/030786 | Method of forming metal wiring for high voltage element | Jan 6, 2005 | Issued |
Array
(
[id] => 7036892
[patent_doc_number] => 20050156326
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'Board for mounting BGA semiconductor chip thereon, semiconductor device, and methods of fabricating such board and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/029676
[patent_app_country] => US
[patent_app_date] => 2005-01-06
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0156/20050156326.pdf
[firstpage_image] =>[orig_patent_app_number] => 11029676
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/029676 | Board for mounting BGA semiconductor chip thereon, semiconductor device, and methods of fabricating such board and semiconductor device | Jan 5, 2005 | Issued |
Array
(
[id] => 7169289
[patent_doc_number] => 20050121803
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Internally reinforced bond pads'
[patent_app_type] => utility
[patent_app_number] => 11/030496
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11030496
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/030496 | Internally reinforced bond pads | Jan 5, 2005 | Issued |
Array
(
[id] => 7253763
[patent_doc_number] => 20050142844
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-30
[patent_title] => 'Method for fabricating metal interconnect in semiconductor device'
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[patent_app_number] => 11/026916
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[firstpage_image] =>[orig_patent_app_number] => 11026916
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/026916 | Method for fabricating metal interconnect in semiconductor device | Dec 29, 2004 | Abandoned |
Array
(
[id] => 7253840
[patent_doc_number] => 20050142865
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[patent_title] => 'Methods of fabricating via hole and trench'
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Array
(
[id] => 386619
[patent_doc_number] => 07303988
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[patent_title] => 'Methods of manufacturing multi-level metal lines in semiconductor devices'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/027035 | Methods of manufacturing multi-level metal lines in semiconductor devices | Dec 29, 2004 | Issued |
Array
(
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Array
(
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Array
(
[id] => 860212
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[patent_title] => 'Manufacturing method of a semiconductor device'
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Array
(
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/009496 | Pitch reduction integrating formation of memory array and peripheral circuitry | Dec 9, 2004 | Issued |