Search

James M. Mitchell

Supervisory Patent Examiner (ID: 19356, Phone: (571)272-1931 , Office: P/4100 )

Most Active Art Unit
2813
Art Unit(s)
4100, 2827, 2822, 2813, 4127
Total Applications
769
Issued Applications
540
Pending Applications
13
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 641704 [patent_doc_number] => 07122403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Method of interconnecting die and substrate' [patent_app_type] => utility [patent_app_number] => 11/010123 [patent_app_country] => US [patent_app_date] => 2004-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2243 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/122/07122403.pdf [firstpage_image] =>[orig_patent_app_number] => 11010123 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/010123
Method of interconnecting die and substrate Dec 9, 2004 Issued
Array ( [id] => 7101484 [patent_doc_number] => 20050104210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Use of palladium in IC manufacturing with conductive polymer bump' [patent_app_type] => utility [patent_app_number] => 11/008654 [patent_app_country] => US [patent_app_date] => 2004-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3805 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20050104210.pdf [firstpage_image] =>[orig_patent_app_number] => 11008654 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/008654
Use of palladium in IC manufacturing with conductive polymer bump Dec 8, 2004 Abandoned
Array ( [id] => 899928 [patent_doc_number] => 07338884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-04 [patent_title] => 'Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/997986 [patent_app_country] => US [patent_app_date] => 2004-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 10987 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/338/07338884.pdf [firstpage_image] =>[orig_patent_app_number] => 10997986 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997986
Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device Nov 28, 2004 Issued
Array ( [id] => 7039525 [patent_doc_number] => 20050158932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/995296 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4827 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20050158932.pdf [firstpage_image] =>[orig_patent_app_number] => 10995296 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/995296
Method of manufacturing semiconductor device Nov 23, 2004 Abandoned
Array ( [id] => 7101387 [patent_doc_number] => 20050104113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Electrode forming method, capacitor element and fabricating method therefor' [patent_app_type] => utility [patent_app_number] => 10/986316 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7538 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20050104113.pdf [firstpage_image] =>[orig_patent_app_number] => 10986316 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/986316
Electrode forming method, capacitor element and fabricating method therefor Nov 11, 2004 Abandoned
Array ( [id] => 151708 [patent_doc_number] => 07678682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'Ultraviolet assisted pore sealing of porous low k dielectric films' [patent_app_type] => utility [patent_app_number] => 10/987276 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/678/07678682.pdf [firstpage_image] =>[orig_patent_app_number] => 10987276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/987276
Ultraviolet assisted pore sealing of porous low k dielectric films Nov 11, 2004 Issued
Array ( [id] => 6905666 [patent_doc_number] => 20050101061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Transfer mold semiconductor packaging processes, circuit substrates, semiconductor packages, and ball grid arrays' [patent_app_type] => utility [patent_app_number] => 10/986424 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2284 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20050101061.pdf [firstpage_image] =>[orig_patent_app_number] => 10986424 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/986424
Transfer mold semiconductor packaging processes Nov 9, 2004 Issued
Array ( [id] => 914216 [patent_doc_number] => 07326590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-05 [patent_title] => 'Method for manufacturing ball grid array package' [patent_app_type] => utility [patent_app_number] => 10/974772 [patent_app_country] => US [patent_app_date] => 2004-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1747 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/326/07326590.pdf [firstpage_image] =>[orig_patent_app_number] => 10974772 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/974772
Method for manufacturing ball grid array package Oct 27, 2004 Issued
Array ( [id] => 7978675 [patent_doc_number] => 08072085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Semiconductor device with plastic package molding compound, semiconductor chip and leadframe and method for producing the same' [patent_app_type] => utility [patent_app_number] => 10/577173 [patent_app_country] => US [patent_app_date] => 2004-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4198 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/072/08072085.pdf [firstpage_image] =>[orig_patent_app_number] => 10577173 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/577173
Semiconductor device with plastic package molding compound, semiconductor chip and leadframe and method for producing the same Oct 24, 2004 Issued
Array ( [id] => 7198810 [patent_doc_number] => 20050051882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Stacked chip package having upper chip provided with trenches and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/962591 [patent_app_country] => US [patent_app_date] => 2004-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3230 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20050051882.pdf [firstpage_image] =>[orig_patent_app_number] => 10962591 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/962591
Stacked chip package having upper chip provided with trenches and method of manufacturing the same Oct 12, 2004 Issued
Array ( [id] => 634557 [patent_doc_number] => 07129562 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-31 [patent_title] => 'Dual-height cell with variable width power rail architecture' [patent_app_type] => utility [patent_app_number] => 10/956689 [patent_app_country] => US [patent_app_date] => 2004-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3355 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/129/07129562.pdf [firstpage_image] =>[orig_patent_app_number] => 10956689 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/956689
Dual-height cell with variable width power rail architecture Sep 30, 2004 Issued
Array ( [id] => 681178 [patent_doc_number] => 07084517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Semiconductor device connecting structure, liquid crystal display unit based on the same connecting structure, and electronic apparatus using the same display unit' [patent_app_type] => utility [patent_app_number] => 10/955798 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5018 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084517.pdf [firstpage_image] =>[orig_patent_app_number] => 10955798 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/955798
Semiconductor device connecting structure, liquid crystal display unit based on the same connecting structure, and electronic apparatus using the same display unit Sep 29, 2004 Issued
Array ( [id] => 7080570 [patent_doc_number] => 20050045950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Semiconductor device and method of fabricating same' [patent_app_type] => utility [patent_app_number] => 10/951593 [patent_app_country] => US [patent_app_date] => 2004-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4291 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20050045950.pdf [firstpage_image] =>[orig_patent_app_number] => 10951593 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/951593
Semiconductor device and method of fabricating same Sep 28, 2004 Issued
Array ( [id] => 7601455 [patent_doc_number] => 07385249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-10 [patent_title] => 'Transistor structure and integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/952010 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2233 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/385/07385249.pdf [firstpage_image] =>[orig_patent_app_number] => 10952010 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/952010
Transistor structure and integrated circuit Sep 27, 2004 Issued
Array ( [id] => 7114420 [patent_doc_number] => 20050067720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Method of forming an encapsulation layer on a back side of a wafer' [patent_app_type] => utility [patent_app_number] => 10/949212 [patent_app_country] => US [patent_app_date] => 2004-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1723 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20050067720.pdf [firstpage_image] =>[orig_patent_app_number] => 10949212 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/949212
Method of forming an encapsulation layer on a back side of a wafer Sep 26, 2004 Abandoned
Array ( [id] => 7010908 [patent_doc_number] => 20050064624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Method of manufacturing wafer level chip size package' [patent_app_type] => utility [patent_app_number] => 10/939416 [patent_app_country] => US [patent_app_date] => 2004-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1532 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20050064624.pdf [firstpage_image] =>[orig_patent_app_number] => 10939416 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/939416
Method of manufacturing wafer level chip size package Sep 13, 2004 Abandoned
Array ( [id] => 5727003 [patent_doc_number] => 20060057763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Method of forming a surface mountable IC and its assembly' [patent_app_type] => utility [patent_app_number] => 10/940436 [patent_app_country] => US [patent_app_date] => 2004-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2594 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20060057763.pdf [firstpage_image] =>[orig_patent_app_number] => 10940436 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/940436
Method of forming a surface mountable IC and its assembly Sep 13, 2004 Abandoned
Array ( [id] => 627013 [patent_doc_number] => 07135396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-14 [patent_title] => 'Method of making a semiconductor structure' [patent_app_type] => utility [patent_app_number] => 10/939775 [patent_app_country] => US [patent_app_date] => 2004-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 4816 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/135/07135396.pdf [firstpage_image] =>[orig_patent_app_number] => 10939775 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/939775
Method of making a semiconductor structure Sep 12, 2004 Issued
Array ( [id] => 847111 [patent_doc_number] => 07384811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-10 [patent_title] => 'Method of separating semiconductor wafer, and separating apparatus using the same' [patent_app_type] => utility [patent_app_number] => 10/938645 [patent_app_country] => US [patent_app_date] => 2004-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4425 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/384/07384811.pdf [firstpage_image] =>[orig_patent_app_number] => 10938645 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/938645
Method of separating semiconductor wafer, and separating apparatus using the same Sep 12, 2004 Issued
Array ( [id] => 7033761 [patent_doc_number] => 20050032271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Lead frame, semiconductor device using the same and method of producing the semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/936795 [patent_app_country] => US [patent_app_date] => 2004-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 2962 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20050032271.pdf [firstpage_image] =>[orig_patent_app_number] => 10936795 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/936795
Lead frame, semiconductor device using the same and method of producing the semiconductor device Sep 8, 2004 Issued
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