
James M. Mitchell
Supervisory Patent Examiner (ID: 15731, Phone: (571)272-1931 , Office: P/4100 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813, 4100, 2827, 2822, 4127 |
| Total Applications | 769 |
| Issued Applications | 540 |
| Pending Applications | 13 |
| Abandoned Applications | 218 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7217626
[patent_doc_number] => 20040154956
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-12
[patent_title] => 'Stacked die module and techniques for forming a stacked die module'
[patent_app_type] => new
[patent_app_number] => 10/770919
[patent_app_country] => US
[patent_app_date] => 2004-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4975
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0154/20040154956.pdf
[firstpage_image] =>[orig_patent_app_number] => 10770919
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/770919 | Stacked die module and techniques for forming a stacked die module | Feb 2, 2004 | Abandoned |
Array
(
[id] => 7002486
[patent_doc_number] => 20050167799
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-04
[patent_title] => 'Method of fabricating wafer-level packaging with sidewall passivation and related apparatus'
[patent_app_type] => utility
[patent_app_number] => 10/767952
[patent_app_country] => US
[patent_app_date] => 2004-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4440
[patent_no_of_claims] => 58
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0167/20050167799.pdf
[firstpage_image] =>[orig_patent_app_number] => 10767952
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/767952 | Method of fabricating wafer-level packaging with sidewall passivation and related apparatus | Jan 28, 2004 | Issued |
Array
(
[id] => 7260313
[patent_doc_number] => 20040150083
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-05
[patent_title] => 'Method for manufacturing digital micro-mirror device (DMD)'
[patent_app_type] => new
[patent_app_number] => 10/761835
[patent_app_country] => US
[patent_app_date] => 2004-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4142
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0150/20040150083.pdf
[firstpage_image] =>[orig_patent_app_number] => 10761835
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/761835 | Method for manufacturing digital micro-mirror device (DMD) | Jan 19, 2004 | Abandoned |
Array
(
[id] => 7287303
[patent_doc_number] => 20040147099
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-29
[patent_title] => 'Method of producing semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/756403
[patent_app_country] => US
[patent_app_date] => 2004-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 9229
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0147/20040147099.pdf
[firstpage_image] =>[orig_patent_app_number] => 10756403
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/756403 | Method of producing semiconductor device | Jan 13, 2004 | Abandoned |
Array
(
[id] => 7673297
[patent_doc_number] => 20040180482
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-16
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => new
[patent_app_number] => 10/756805
[patent_app_country] => US
[patent_app_date] => 2004-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5244
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0180/20040180482.pdf
[firstpage_image] =>[orig_patent_app_number] => 10756805
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/756805 | Semiconductor device and manufacturing method thereof | Jan 12, 2004 | Abandoned |
Array
(
[id] => 6983416
[patent_doc_number] => 20050153486
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-14
[patent_title] => 'Method of fabricating a strained silicon channel FinFET'
[patent_app_type] => utility
[patent_app_number] => 10/755763
[patent_app_country] => US
[patent_app_date] => 2004-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 4546
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0153/20050153486.pdf
[firstpage_image] =>[orig_patent_app_number] => 10755763
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/755763 | Method of fabricating an integrated circuit channel region | Jan 11, 2004 | Issued |
Array
(
[id] => 7309218
[patent_doc_number] => 20040142523
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-22
[patent_title] => 'Method of forming vertical mosfet with ultra-low on-resistance and low gate charge'
[patent_app_type] => new
[patent_app_number] => 10/754276
[patent_app_country] => US
[patent_app_date] => 2004-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4128
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0142/20040142523.pdf
[firstpage_image] =>[orig_patent_app_number] => 10754276
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/754276 | Method of forming vertical mosfet with ultra-low on-resistance and low gate charge | Jan 7, 2004 | Abandoned |
Array
(
[id] => 833776
[patent_doc_number] => 07397067
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-08
[patent_title] => 'Microdisplay packaging system'
[patent_app_type] => utility
[patent_app_number] => 10/750308
[patent_app_country] => US
[patent_app_date] => 2003-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 4022
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/397/07397067.pdf
[firstpage_image] =>[orig_patent_app_number] => 10750308
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/750308 | Microdisplay packaging system | Dec 30, 2003 | Issued |
Array
(
[id] => 7387879
[patent_doc_number] => 20040172813
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-09
[patent_title] => 'Method for manufacturing semiconductor device, semiconductor device, circuit board, and electronic apparatus'
[patent_app_type] => new
[patent_app_number] => 10/744702
[patent_app_country] => US
[patent_app_date] => 2003-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7142
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0172/20040172813.pdf
[firstpage_image] =>[orig_patent_app_number] => 10744702
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/744702 | Method for manufacturing semiconductor device, semiconductor device, circuit board, and electronic apparatus | Dec 22, 2003 | Issued |
Array
(
[id] => 6996802
[patent_doc_number] => 20050136580
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-23
[patent_title] => 'Hydrogen free formation of gate electrodes'
[patent_app_type] => utility
[patent_app_number] => 10/745313
[patent_app_country] => US
[patent_app_date] => 2003-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4718
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0136/20050136580.pdf
[firstpage_image] =>[orig_patent_app_number] => 10745313
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/745313 | Hydrogen free formation of gate electrodes | Dec 21, 2003 | Abandoned |
Array
(
[id] => 536299
[patent_doc_number] => 07180195
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-20
[patent_title] => 'Method and apparatus for improved power routing'
[patent_app_type] => utility
[patent_app_number] => 10/739726
[patent_app_country] => US
[patent_app_date] => 2003-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3219
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/180/07180195.pdf
[firstpage_image] =>[orig_patent_app_number] => 10739726
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/739726 | Method and apparatus for improved power routing | Dec 16, 2003 | Issued |
Array
(
[id] => 7295964
[patent_doc_number] => 20040124513
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-01
[patent_title] => 'High-density multichip module package'
[patent_app_type] => new
[patent_app_number] => 10/734195
[patent_app_country] => US
[patent_app_date] => 2003-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2102
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20040124513.pdf
[firstpage_image] =>[orig_patent_app_number] => 10734195
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/734195 | High-density multichip module package | Dec 14, 2003 | Abandoned |
Array
(
[id] => 616774
[patent_doc_number] => 07145187
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-12-05
[patent_title] => 'Substrate independent multiple input bi-directional ESD protection structure'
[patent_app_type] => utility
[patent_app_number] => 10/735500
[patent_app_country] => US
[patent_app_date] => 2003-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3213
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/145/07145187.pdf
[firstpage_image] =>[orig_patent_app_number] => 10735500
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/735500 | Substrate independent multiple input bi-directional ESD protection structure | Dec 11, 2003 | Issued |
Array
(
[id] => 7370864
[patent_doc_number] => 20040079862
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-29
[patent_title] => 'Two part mold for wafer scale caps'
[patent_app_type] => new
[patent_app_number] => 10/728808
[patent_app_country] => US
[patent_app_date] => 2003-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5152
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0079/20040079862.pdf
[firstpage_image] =>[orig_patent_app_number] => 10728808
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/728808 | Two part mold for wafer scale caps | Dec 7, 2003 | Issued |
Array
(
[id] => 7383112
[patent_doc_number] => 20040082105
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-29
[patent_title] => 'Wafer scale caps located by molding'
[patent_app_type] => new
[patent_app_number] => 10/728800
[patent_app_country] => US
[patent_app_date] => 2003-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5171
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0082/20040082105.pdf
[firstpage_image] =>[orig_patent_app_number] => 10728800
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/728800 | Wafer scale caps located by molding | Dec 7, 2003 | Issued |
Array
(
[id] => 7466705
[patent_doc_number] => 20040101992
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-27
[patent_title] => 'Chips with wafer scale caps formed by molding'
[patent_app_type] => new
[patent_app_number] => 10/728929
[patent_app_country] => US
[patent_app_date] => 2003-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5172
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0101/20040101992.pdf
[firstpage_image] =>[orig_patent_app_number] => 10728929
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/728929 | Chips with wafer scale caps formed by molding | Dec 7, 2003 | Issued |
Array
(
[id] => 7471330
[patent_doc_number] => 20040121517
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-24
[patent_title] => 'Placement tool for wafer scale caps'
[patent_app_type] => new
[patent_app_number] => 10/728985
[patent_app_country] => US
[patent_app_date] => 2003-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5172
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0121/20040121517.pdf
[firstpage_image] =>[orig_patent_app_number] => 10728985
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/728985 | Placement tool for wafer scale caps | Dec 7, 2003 | Issued |
Array
(
[id] => 744523
[patent_doc_number] => 07026176
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-11
[patent_title] => 'Mold making method for wafer scale caps'
[patent_app_type] => utility
[patent_app_number] => 10/728923
[patent_app_country] => US
[patent_app_date] => 2003-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 23
[patent_no_of_words] => 5109
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/026/07026176.pdf
[firstpage_image] =>[orig_patent_app_number] => 10728923
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/728923 | Mold making method for wafer scale caps | Dec 7, 2003 | Issued |
Array
(
[id] => 7406411
[patent_doc_number] => 20040175866
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-09
[patent_title] => 'Plastic housing comprising several semiconductor chips and a wiring modification plate, and method for producing the plastic housing in an injection-molding mold'
[patent_app_type] => new
[patent_app_number] => 10/478682
[patent_app_country] => US
[patent_app_date] => 2003-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6099
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0175/20040175866.pdf
[firstpage_image] =>[orig_patent_app_number] => 10478682
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/478682 | Plastic housing comprising several semiconductor chips and a wiring modification plate, and method for producing the plastic housing in an injection-molding mold | Dec 4, 2003 | Abandoned |
Array
(
[id] => 7178802
[patent_doc_number] => 20050124127
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Method for manufacturing gate structure for use in semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/726500
[patent_app_country] => US
[patent_app_date] => 2003-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2062
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20050124127.pdf
[firstpage_image] =>[orig_patent_app_number] => 10726500
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/726500 | Method for manufacturing gate structure for use in semiconductor device | Dec 3, 2003 | Abandoned |