
James M. Mitchell
Supervisory Patent Examiner (ID: 15731, Phone: (571)272-1931 , Office: P/4100 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813, 4100, 2827, 2822, 4127 |
| Total Applications | 769 |
| Issued Applications | 540 |
| Pending Applications | 13 |
| Abandoned Applications | 218 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7116769
[patent_doc_number] => 20050070070
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-31
[patent_title] => 'METHOD OF FORMING STRAINED SILICON ON INSULATOR'
[patent_app_type] => utility
[patent_app_number] => 10/605408
[patent_app_country] => US
[patent_app_date] => 2003-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3203
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0070/20050070070.pdf
[firstpage_image] =>[orig_patent_app_number] => 10605408
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/605408 | METHOD OF FORMING STRAINED SILICON ON INSULATOR | Sep 28, 2003 | Abandoned |
Array
(
[id] => 7267824
[patent_doc_number] => 20040056342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-25
[patent_title] => 'Stacked die module and techniques for forming a stacked die module'
[patent_app_type] => new
[patent_app_number] => 10/672750
[patent_app_country] => US
[patent_app_date] => 2003-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4917
[patent_no_of_claims] => 62
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 12
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0056/20040056342.pdf
[firstpage_image] =>[orig_patent_app_number] => 10672750
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/672750 | Stacked die module including multiple adhesives that cure at different temperatures | Sep 24, 2003 | Issued |
Array
(
[id] => 7375730
[patent_doc_number] => 20040178514
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-16
[patent_title] => 'Method of encapsulating semiconductor devices on a printed circuit board, and a printed circuit board for use in the method'
[patent_app_type] => new
[patent_app_number] => 10/665632
[patent_app_country] => US
[patent_app_date] => 2003-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4177
[patent_no_of_claims] => 61
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0178/20040178514.pdf
[firstpage_image] =>[orig_patent_app_number] => 10665632
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/665632 | Method of encapsulating semiconductor devices on a printed circuit board, and a printed circuit board for use in the method | Sep 21, 2003 | Abandoned |
Array
(
[id] => 480221
[patent_doc_number] => 07224057
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-29
[patent_title] => 'Thermal enhance package with universal heat spreader'
[patent_app_type] => utility
[patent_app_number] => 10/657132
[patent_app_country] => US
[patent_app_date] => 2003-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2008
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/224/07224057.pdf
[firstpage_image] =>[orig_patent_app_number] => 10657132
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/657132 | Thermal enhance package with universal heat spreader | Sep 8, 2003 | Issued |
Array
(
[id] => 916970
[patent_doc_number] => 07323358
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-01-29
[patent_title] => 'Method and system for sizing a load plate'
[patent_app_type] => utility
[patent_app_number] => 10/639853
[patent_app_country] => US
[patent_app_date] => 2003-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2834
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/323/07323358.pdf
[firstpage_image] =>[orig_patent_app_number] => 10639853
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/639853 | Method and system for sizing a load plate | Aug 12, 2003 | Issued |
Array
(
[id] => 7220024
[patent_doc_number] => 20040155358
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-12
[patent_title] => 'First and second level packaging assemblies and method of assembling package'
[patent_app_type] => new
[patent_app_number] => 10/635538
[patent_app_country] => US
[patent_app_date] => 2003-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8314
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0155/20040155358.pdf
[firstpage_image] =>[orig_patent_app_number] => 10635538
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/635538 | First and second level packaging assemblies and method of assembling package | Aug 6, 2003 | Abandoned |
Array
(
[id] => 7033719
[patent_doc_number] => 20050032229
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-10
[patent_title] => 'PROBE TIP DESIGN APPLIED IN A FLIP CHIP PACKAGING PROCESS'
[patent_app_type] => utility
[patent_app_number] => 10/604611
[patent_app_country] => US
[patent_app_date] => 2003-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 2570
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0032/20050032229.pdf
[firstpage_image] =>[orig_patent_app_number] => 10604611
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604611 | PROBE TIP DESIGN APPLIED IN A FLIP CHIP PACKAGING PROCESS | Aug 4, 2003 | Abandoned |
Array
(
[id] => 524933
[patent_doc_number] => 07183130
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-27
[patent_title] => 'Magnetic random access memory and method of fabricating thereof'
[patent_app_type] => utility
[patent_app_number] => 10/604533
[patent_app_country] => US
[patent_app_date] => 2003-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 2579
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/183/07183130.pdf
[firstpage_image] =>[orig_patent_app_number] => 10604533
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/604533 | Magnetic random access memory and method of fabricating thereof | Jul 28, 2003 | Issued |
Array
(
[id] => 690516
[patent_doc_number] => 07074696
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-07-11
[patent_title] => 'Semiconductor circuit module and method for fabricating semiconductor circuit modules'
[patent_app_type] => utility
[patent_app_number] => 10/630632
[patent_app_country] => US
[patent_app_date] => 2003-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 24
[patent_no_of_words] => 3515
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/074/07074696.pdf
[firstpage_image] =>[orig_patent_app_number] => 10630632
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/630632 | Semiconductor circuit module and method for fabricating semiconductor circuit modules | Jul 28, 2003 | Issued |
Array
(
[id] => 956207
[patent_doc_number] => 06955957
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-10-18
[patent_title] => 'Method of forming a floating gate in a flash memory device'
[patent_app_type] => utility
[patent_app_number] => 10/616508
[patent_app_country] => US
[patent_app_date] => 2003-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2112
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/955/06955957.pdf
[firstpage_image] =>[orig_patent_app_number] => 10616508
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/616508 | Method of forming a floating gate in a flash memory device | Jul 9, 2003 | Issued |
Array
(
[id] => 7058951
[patent_doc_number] => 20050001310
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => 'Supporting a circuit package including a substrate having a solder column array'
[patent_app_type] => utility
[patent_app_number] => 10/612663
[patent_app_country] => US
[patent_app_date] => 2003-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3635
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20050001310.pdf
[firstpage_image] =>[orig_patent_app_number] => 10612663
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/612663 | Supporting a circuit package including a substrate having a solder column array | Jul 1, 2003 | Issued |
Array
(
[id] => 7414814
[patent_doc_number] => 20040264148
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-30
[patent_title] => 'Method and system for fan fold packaging'
[patent_app_type] => new
[patent_app_number] => 10/609052
[patent_app_country] => US
[patent_app_date] => 2003-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2647
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0264/20040264148.pdf
[firstpage_image] =>[orig_patent_app_number] => 10609052
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/609052 | Method and system for fan fold packaging | Jun 26, 2003 | Abandoned |
Array
(
[id] => 7190025
[patent_doc_number] => 20040084781
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-06
[patent_title] => 'Compact system module with built-in thermoelectric cooling'
[patent_app_type] => new
[patent_app_number] => 10/606539
[patent_app_country] => US
[patent_app_date] => 2003-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8380
[patent_no_of_claims] => 82
[patent_no_of_ind_claims] => 17
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0084/20040084781.pdf
[firstpage_image] =>[orig_patent_app_number] => 10606539
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/606539 | Compact system module with built-in thermoelectric cooling | Jun 25, 2003 | Issued |
Array
(
[id] => 6612104
[patent_doc_number] => 20030209799
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-13
[patent_title] => 'Copper plated PTH barrels and methods for fabricating'
[patent_app_type] => new
[patent_app_number] => 10/461516
[patent_app_country] => US
[patent_app_date] => 2003-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5427
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0209/20030209799.pdf
[firstpage_image] =>[orig_patent_app_number] => 10461516
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/461516 | Copper plated PTH barrels and methods for fabricating | Jun 15, 2003 | Abandoned |
Array
(
[id] => 1043647
[patent_doc_number] => 06867080
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-03-15
[patent_title] => 'Polysilicon tilting to prevent geometry effects during laser thermal annealing'
[patent_app_type] => utility
[patent_app_number] => 10/460165
[patent_app_country] => US
[patent_app_date] => 2003-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2871
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/867/06867080.pdf
[firstpage_image] =>[orig_patent_app_number] => 10460165
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/460165 | Polysilicon tilting to prevent geometry effects during laser thermal annealing | Jun 12, 2003 | Issued |
Array
(
[id] => 1012621
[patent_doc_number] => 06897092
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-24
[patent_title] => 'Method of supporting a substrate film'
[patent_app_type] => utility
[patent_app_number] => 10/461548
[patent_app_country] => US
[patent_app_date] => 2003-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 6251
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/897/06897092.pdf
[firstpage_image] =>[orig_patent_app_number] => 10461548
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/461548 | Method of supporting a substrate film | Jun 11, 2003 | Issued |
Array
(
[id] => 7212788
[patent_doc_number] => 20050054179
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-10
[patent_title] => 'Method and apparatus for splitting semiconductor wafer'
[patent_app_type] => utility
[patent_app_number] => 10/485776
[patent_app_country] => US
[patent_app_date] => 2003-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5492
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0054/20050054179.pdf
[firstpage_image] =>[orig_patent_app_number] => 10485776
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/485776 | Method and apparatus for splitting semiconductor wafer | Jun 9, 2003 | Abandoned |
Array
(
[id] => 690357
[patent_doc_number] => 07074623
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-11
[patent_title] => 'Methods of forming strained-semiconductor-on-insulator finFET device structures'
[patent_app_type] => utility
[patent_app_number] => 10/456708
[patent_app_country] => US
[patent_app_date] => 2003-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 46
[patent_figures_cnt] => 59
[patent_no_of_words] => 15767
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/074/07074623.pdf
[firstpage_image] =>[orig_patent_app_number] => 10456708
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/456708 | Methods of forming strained-semiconductor-on-insulator finFET device structures | Jun 5, 2003 | Issued |
Array
(
[id] => 931087
[patent_doc_number] => 06979591
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-12-27
[patent_title] => 'Connection of integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 10/446396
[patent_app_country] => US
[patent_app_date] => 2003-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 17
[patent_no_of_words] => 3323
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/979/06979591.pdf
[firstpage_image] =>[orig_patent_app_number] => 10446396
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/446396 | Connection of integrated circuits | May 27, 2003 | Issued |
Array
(
[id] => 766213
[patent_doc_number] => 07008825
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-03-07
[patent_title] => 'Leadframe strip having enhanced testability'
[patent_app_type] => utility
[patent_app_number] => 10/445754
[patent_app_country] => US
[patent_app_date] => 2003-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 7432
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/008/07008825.pdf
[firstpage_image] =>[orig_patent_app_number] => 10445754
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/445754 | Leadframe strip having enhanced testability | May 26, 2003 | Issued |