
James M. Mitchell
Supervisory Patent Examiner (ID: 15731, Phone: (571)272-1931 , Office: P/4100 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813, 4100, 2827, 2822, 4127 |
| Total Applications | 769 |
| Issued Applications | 540 |
| Pending Applications | 13 |
| Abandoned Applications | 218 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8177055
[patent_doc_number] => 08178435
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-05-15
[patent_title] => 'High performance system-on-chip inductor using post passivation process'
[patent_app_type] => utility
[patent_app_number] => 10/445558
[patent_app_country] => US
[patent_app_date] => 2003-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 40
[patent_no_of_words] => 8822
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 292
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/178/08178435.pdf
[firstpage_image] =>[orig_patent_app_number] => 10445558
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/445558 | High performance system-on-chip inductor using post passivation process | May 26, 2003 | Issued |
Array
(
[id] => 7273111
[patent_doc_number] => 20040232562
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-11-25
[patent_title] => 'System and method for increasing bump pad height'
[patent_app_type] => new
[patent_app_number] => 10/445164
[patent_app_country] => US
[patent_app_date] => 2003-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2471
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0232/20040232562.pdf
[firstpage_image] =>[orig_patent_app_number] => 10445164
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/445164 | System and method for increasing bump pad height | May 22, 2003 | Abandoned |
Array
(
[id] => 1017942
[patent_doc_number] => 06890836
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-10
[patent_title] => 'Scribe street width reduction by deep trench and shallow saw cut'
[patent_app_type] => utility
[patent_app_number] => 10/445163
[patent_app_country] => US
[patent_app_date] => 2003-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3781
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/890/06890836.pdf
[firstpage_image] =>[orig_patent_app_number] => 10445163
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/445163 | Scribe street width reduction by deep trench and shallow saw cut | May 22, 2003 | Issued |
Array
(
[id] => 7421223
[patent_doc_number] => 20040000707
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-01
[patent_title] => 'Modularized die stacking system and method'
[patent_app_type] => new
[patent_app_number] => 10/435192
[patent_app_country] => US
[patent_app_date] => 2003-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6017
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0000/20040000707.pdf
[firstpage_image] =>[orig_patent_app_number] => 10435192
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/435192 | Modularized die stacking system and method | May 8, 2003 | Issued |
Array
(
[id] => 728232
[patent_doc_number] => 07041513
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-09
[patent_title] => 'Methods for forming semiconductor devices so as to stabilize the same when positioned face-down over test substrates'
[patent_app_type] => utility
[patent_app_number] => 10/430753
[patent_app_country] => US
[patent_app_date] => 2003-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 21
[patent_no_of_words] => 10126
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/041/07041513.pdf
[firstpage_image] =>[orig_patent_app_number] => 10430753
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/430753 | Methods for forming semiconductor devices so as to stabilize the same when positioned face-down over test substrates | May 5, 2003 | Issued |
Array
(
[id] => 7296428
[patent_doc_number] => 20040214377
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-28
[patent_title] => 'Low thermal expansion adhesives and encapsulants for cryogenic and high power density electronic and photonic device assembly and packaging'
[patent_app_type] => new
[patent_app_number] => 10/425894
[patent_app_country] => US
[patent_app_date] => 2003-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5319
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0214/20040214377.pdf
[firstpage_image] =>[orig_patent_app_number] => 10425894
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/425894 | Low thermal expansion adhesives and encapsulants for cryogenic and high power density electronic and photonic device assembly and packaging | Apr 27, 2003 | Abandoned |
Array
(
[id] => 6863688
[patent_doc_number] => 20030189214
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-09
[patent_title] => 'Techniques for joining an opto-electronic module to a semiconductor package'
[patent_app_type] => new
[patent_app_number] => 10/412564
[patent_app_country] => US
[patent_app_date] => 2003-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5331
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0189/20030189214.pdf
[firstpage_image] =>[orig_patent_app_number] => 10412564
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/412564 | Techniques for joining an opto-electronic module to a semiconductor package | Apr 10, 2003 | Issued |
Array
(
[id] => 746412
[patent_doc_number] => 07026654
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-11
[patent_title] => 'Package for optical semiconductor'
[patent_app_type] => utility
[patent_app_number] => 10/406943
[patent_app_country] => US
[patent_app_date] => 2003-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 17
[patent_no_of_words] => 3684
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/026/07026654.pdf
[firstpage_image] =>[orig_patent_app_number] => 10406943
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/406943 | Package for optical semiconductor | Apr 2, 2003 | Issued |
Array
(
[id] => 7069666
[patent_doc_number] => 20050245051
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-03
[patent_title] => 'Parting method for fragile material substrate and parting device using the method'
[patent_app_type] => utility
[patent_app_number] => 10/509895
[patent_app_country] => US
[patent_app_date] => 2003-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 28666
[patent_no_of_claims] => 54
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0245/20050245051.pdf
[firstpage_image] =>[orig_patent_app_number] => 10509895
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/509895 | Method for severing brittle material substrate and severing apparatus using the method | Mar 31, 2003 | Issued |
Array
(
[id] => 869685
[patent_doc_number] => 07365442
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-04-29
[patent_title] => 'Encapsulation of thin-film electronic devices'
[patent_app_type] => utility
[patent_app_number] => 10/403565
[patent_app_country] => US
[patent_app_date] => 2003-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4048
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/365/07365442.pdf
[firstpage_image] =>[orig_patent_app_number] => 10403565
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/403565 | Encapsulation of thin-film electronic devices | Mar 30, 2003 | Issued |
Array
(
[id] => 6785809
[patent_doc_number] => 20030137048
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-24
[patent_title] => 'Stacking system and method'
[patent_app_type] => new
[patent_app_number] => 10/400309
[patent_app_country] => US
[patent_app_date] => 2003-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 7274
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 28
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0137/20030137048.pdf
[firstpage_image] =>[orig_patent_app_number] => 10400309
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/400309 | Stacking system and method | Mar 26, 2003 | Abandoned |
Array
(
[id] => 7285556
[patent_doc_number] => 20040108104
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-10
[patent_title] => 'Axial heat-dissipating device'
[patent_app_type] => new
[patent_app_number] => 10/395933
[patent_app_country] => US
[patent_app_date] => 2003-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 2548
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0108/20040108104.pdf
[firstpage_image] =>[orig_patent_app_number] => 10395933
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/395933 | Axial heat-dissipating device | Mar 23, 2003 | Abandoned |
Array
(
[id] => 743012
[patent_doc_number] => 07030502
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-18
[patent_title] => 'BGA package with same power ballout assignment for wire bonding packaging and flip chip packaging'
[patent_app_type] => utility
[patent_app_number] => 10/249179
[patent_app_country] => US
[patent_app_date] => 2003-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6098
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 285
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/030/07030502.pdf
[firstpage_image] =>[orig_patent_app_number] => 10249179
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/249179 | BGA package with same power ballout assignment for wire bonding packaging and flip chip packaging | Mar 19, 2003 | Issued |
Array
(
[id] => 6834776
[patent_doc_number] => 20030162322
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-28
[patent_title] => 'Semiconductor wafer having a thin die and tethers and methods of making the same'
[patent_app_type] => new
[patent_app_number] => 10/387754
[patent_app_country] => US
[patent_app_date] => 2003-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8351
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0162/20030162322.pdf
[firstpage_image] =>[orig_patent_app_number] => 10387754
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/387754 | Semiconductor wafer having a thin die and tethers and methods of making the same | Mar 12, 2003 | Issued |
Array
(
[id] => 1034422
[patent_doc_number] => 06875631
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-05
[patent_title] => 'Semiconductor device and a method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 10/360712
[patent_app_country] => US
[patent_app_date] => 2003-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 23
[patent_no_of_words] => 3407
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 384
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/875/06875631.pdf
[firstpage_image] =>[orig_patent_app_number] => 10360712
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/360712 | Semiconductor device and a method of manufacturing the same | Feb 9, 2003 | Issued |
Array
(
[id] => 447737
[patent_doc_number] => 07253510
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-07
[patent_title] => 'Ball grid array package construction with raised solder ball pads'
[patent_app_type] => utility
[patent_app_number] => 10/346277
[patent_app_country] => US
[patent_app_date] => 2003-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4368
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 285
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/253/07253510.pdf
[firstpage_image] =>[orig_patent_app_number] => 10346277
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/346277 | Ball grid array package construction with raised solder ball pads | Jan 15, 2003 | Issued |
Array
(
[id] => 6696887
[patent_doc_number] => 20030109081
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-12
[patent_title] => 'Ozone treatment of a ground semiconductor die to improve adhesive bonding to a substrate'
[patent_app_type] => new
[patent_app_number] => 10/341610
[patent_app_country] => US
[patent_app_date] => 2003-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5302
[patent_no_of_claims] => 87
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0109/20030109081.pdf
[firstpage_image] =>[orig_patent_app_number] => 10341610
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/341610 | Treatment of a ground semiconductor die to improve adhesive bonding to a substrate | Jan 12, 2003 | Issued |
Array
(
[id] => 6628118
[patent_doc_number] => 20030102566
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-05
[patent_title] => 'Stereolithographic method for applying materials to electronic component substrates and resulting structures'
[patent_app_type] => new
[patent_app_number] => 10/338602
[patent_app_country] => US
[patent_app_date] => 2003-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6230
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0102/20030102566.pdf
[firstpage_image] =>[orig_patent_app_number] => 10338602
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/338602 | Stereolithographic method for applying materials to electronic component substrates and resulting structures | Jan 7, 2003 | Abandoned |
Array
(
[id] => 6851616
[patent_doc_number] => 20030143819
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-31
[patent_title] => 'Method of producing semiconductor chips with a chip edge guard, in particular for wafer level packaging chips'
[patent_app_type] => new
[patent_app_number] => 10/336373
[patent_app_country] => US
[patent_app_date] => 2003-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2911
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 14
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0143/20030143819.pdf
[firstpage_image] =>[orig_patent_app_number] => 10336373
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/336373 | Method of producing semiconductor chips with a chip edge guard, in particular for wafer level packaging chips | Jan 2, 2003 | Abandoned |
Array
(
[id] => 6623288
[patent_doc_number] => 20030102151
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-06-05
[patent_title] => 'Multilayer build-up wiring board'
[patent_app_type] => new
[patent_app_number] => 10/334062
[patent_app_country] => US
[patent_app_date] => 2002-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
[patent_figures_cnt] => 44
[patent_no_of_words] => 23570
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0102/20030102151.pdf
[firstpage_image] =>[orig_patent_app_number] => 10334062
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/334062 | Multilayer build-up wiring board | Dec 30, 2002 | Issued |