James M. Mitchell

Array ( [id] => 1486794 [patent_doc_number] => 06365961 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'High-frequency input/output feedthrough and package for housing high-frequency semiconductor element using same' [patent_app_type] => B1 [patent_app_number] => 09/484917 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 12493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365961.pdf [firstpage_image] =>[orig_patent_app_number] => 09484917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 793147 [patent_doc_number] => 06982192 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-03 [patent_title] => 'High performance thermal interface curing process for organic flip chip packages' [patent_app_type] => utility [patent_app_number] => 09/475104 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1017 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982192.pdf [firstpage_image] =>[orig_patent_app_number] => 09475104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 961093 [patent_doc_number] => 06951806 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-04 [patent_title] => 'Metal region for reduction of capacitive coupling between signal lines' [patent_app_type] => utility [patent_app_number] => 09/452367 [patent_app_country] => US [patent_app_date] => 1999-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6303 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/951/06951806.pdf [firstpage_image] =>[orig_patent_app_number] => 09452367 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1150273 [patent_doc_number] => 06774474 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Partially captured oriented interconnections for BGA packages and a method of forming the interconnections' [patent_app_type] => B1 [patent_app_number] => 09/438037 [patent_app_country] => US [patent_app_date] => 1999-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 2851 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774474.pdf [firstpage_image] =>[orig_patent_app_number] => 09438037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1529588 [patent_doc_number] => 06479901 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Semiconductor device having interconnected external electrode pads and wire bonding pads' [patent_app_type] => B1 [patent_app_number] => 09/434487 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2245 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479901.pdf [firstpage_image] =>[orig_patent_app_number] => 09434487 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1022565 [patent_doc_number] => 06888230 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-03 [patent_title] => 'Semiconductor device, semiconductor wafer, semiconductor module, and a method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 09/429297 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 32 [patent_no_of_words] => 11896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888230.pdf [firstpage_image] =>[orig_patent_app_number] => 09429297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1491778 [patent_doc_number] => 06417531 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Charge transfer device with final potential well close to floating diffusion region' [patent_app_type] => B1 [patent_app_number] => 09/427977 [patent_app_country] => US [patent_app_date] => 1999-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 61 [patent_no_of_words] => 10902 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417531.pdf [firstpage_image] =>[orig_patent_app_number] => 09427977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1128374 [patent_doc_number] => 06791170 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-14 [patent_title] => 'Onboard semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/419787 [patent_app_country] => US [patent_app_date] => 1999-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 0 [patent_no_of_words] => 3518 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/791/06791170.pdf [firstpage_image] =>[orig_patent_app_number] => 09419787 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1336754 [patent_doc_number] => 06597053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Integrated circuit arrangement with a number of structural elements and method for the production thereof' [patent_app_type] => B1 [patent_app_number] => 09/403157 [patent_app_country] => US [patent_app_date] => 1999-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/597/06597053.pdf [firstpage_image] =>[orig_patent_app_number] => 09403157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7636037 [patent_doc_number] => 06380623 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Microcircuit assembly having dual-path grounding and negative self-bias' [patent_app_type] => B1 [patent_app_number] => 09/418870 [patent_app_country] => US [patent_app_date] => 1999-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2275 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380623.pdf [firstpage_image] =>[orig_patent_app_number] => 09418870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1441339 [patent_doc_number] => 06496053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Corrosion insensitive fusible link using capacitance sensing for semiconductor devices' [patent_app_type] => B1 [patent_app_number] => 09/416977 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 29 [patent_no_of_words] => 5165 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496053.pdf [firstpage_image] =>[orig_patent_app_number] => 09416977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1516210 [patent_doc_number] => 06420774 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Low junction capacitance semiconductor structure and I/O buffer' [patent_app_type] => B1 [patent_app_number] => 09/413407 [patent_app_country] => US [patent_app_date] => 1999-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3639 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420774.pdf [firstpage_image] =>[orig_patent_app_number] => 09413407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1465090 [patent_doc_number] => 06351392 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Offset array adapter' [patent_app_type] => B1 [patent_app_number] => 09/412217 [patent_app_country] => US [patent_app_date] => 1999-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7850 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351392.pdf [firstpage_image] =>[orig_patent_app_number] => 09412217 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1478831 [patent_doc_number] => 06344666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Amplifier-type solid-state image sensor device' [patent_app_type] => B1 [patent_app_number] => 09/407847 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5059 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344666.pdf [firstpage_image] =>[orig_patent_app_number] => 09407847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1404322 [patent_doc_number] => 06541864 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Semiconductor device with tapered contact hole and wire groove' [patent_app_type] => B1 [patent_app_number] => 09/405127 [patent_app_country] => US [patent_app_date] => 1999-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 71 [patent_no_of_words] => 15852 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/541/06541864.pdf [firstpage_image] =>[orig_patent_app_number] => 09405127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1580418 [patent_doc_number] => 06448651 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Semiconductor device having a multi-level metallization and its fabricating method' [patent_app_type] => B1 [patent_app_number] => 09/396147 [patent_app_country] => US [patent_app_date] => 1999-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6057 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448651.pdf [firstpage_image] =>[orig_patent_app_number] => 09396147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 935671 [patent_doc_number] => 06975021 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-13 [patent_title] => 'Carrier for substrate film' [patent_app_type] => utility [patent_app_number] => 09/389720 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6208 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/975/06975021.pdf [firstpage_image] =>[orig_patent_app_number] => 09389720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1587833 [patent_doc_number] => 06359314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Swapped drain structures for electrostatic discharge protection' [patent_app_type] => B1 [patent_app_number] => 09/388727 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4785 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359314.pdf [firstpage_image] =>[orig_patent_app_number] => 09388727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4351175 [patent_doc_number] => 06285077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Multiple layer tape ball grid array package' [patent_app_type] => 1 [patent_app_number] => 9/377887 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1339 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285077.pdf [firstpage_image] =>[orig_patent_app_number] => 377887 [rel_patent_id] =>[rel_patent_doc_number] =>)