Search

James M. Mitchell

Supervisory Patent Examiner (ID: 10382, Phone: (571)272-1931 , Office: P/4100 )

Most Active Art Unit
2813
Art Unit(s)
2813, 2827, 4100, 2822, 4127
Total Applications
769
Issued Applications
540
Pending Applications
13
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8897242 [patent_doc_number] => 08476765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Copper interconnect structure having a graphene cap' [patent_app_type] => utility [patent_app_number] => 12/961251 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2887 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12961251 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/961251
Copper interconnect structure having a graphene cap Dec 5, 2010 Issued
Array ( [id] => 7480148 [patent_doc_number] => 20110248399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-13 [patent_title] => 'Semiconductor Device and Method of Forming High Routing Density Interconnect Sites on Substrate' [patent_app_type] => utility [patent_app_number] => 12/961027 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 19897 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20110248399.pdf [firstpage_image] =>[orig_patent_app_number] => 12961027 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/961027
Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate Dec 5, 2010 Issued
Array ( [id] => 7738927 [patent_doc_number] => 20120018885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'SEMICONDUCTOR APPARATUS HAVING THROUGH VIAS' [patent_app_type] => utility [patent_app_number] => 12/960843 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14738 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20120018885.pdf [firstpage_image] =>[orig_patent_app_number] => 12960843 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/960843
Semiconductor apparatus having through vias configured to isolate power supplied to a memory chip from data signals supplied to the memory chip Dec 5, 2010 Issued
Array ( [id] => 8643201 [patent_doc_number] => 08368189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Auxiliary leadframe member for stabilizing the bond wire process' [patent_app_type] => utility [patent_app_number] => 12/960268 [patent_app_country] => US [patent_app_date] => 2010-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 4222 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12960268 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/960268
Auxiliary leadframe member for stabilizing the bond wire process Dec 2, 2010 Issued
Array ( [id] => 5955888 [patent_doc_number] => 20110180916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'MULTI-CHIP PACKAGE HAVING FRAME INTERPOSER' [patent_app_type] => utility [patent_app_number] => 12/959596 [patent_app_country] => US [patent_app_date] => 2010-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5330 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20110180916.pdf [firstpage_image] =>[orig_patent_app_number] => 12959596 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/959596
Multi-chip package having frame interposer Dec 2, 2010 Issued
Array ( [id] => 9882412 [patent_doc_number] => 08969176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Laminated transferable interconnect for microelectronic package' [patent_app_type] => utility [patent_app_number] => 12/959549 [patent_app_country] => US [patent_app_date] => 2010-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 1714 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12959549 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/959549
Laminated transferable interconnect for microelectronic package Dec 2, 2010 Issued
Array ( [id] => 9086203 [patent_doc_number] => 08557629 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-15 [patent_title] => 'Semiconductor device having overlapped via apertures' [patent_app_type] => utility [patent_app_number] => 12/959911 [patent_app_country] => US [patent_app_date] => 2010-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3582 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12959911 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/959911
Semiconductor device having overlapped via apertures Dec 2, 2010 Issued
Array ( [id] => 8224914 [patent_doc_number] => 20120139112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'Selective Seed Layer Treatment for Feature Plating' [patent_app_type] => utility [patent_app_number] => 12/958638 [patent_app_country] => US [patent_app_date] => 2010-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3050 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12958638 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/958638
Selective seed layer treatment for feature plating Dec 1, 2010 Issued
Array ( [id] => 6210858 [patent_doc_number] => 20110134705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND A MULTIPLEXED COMMUNICATIONS INTERFACE' [patent_app_type] => utility [patent_app_number] => 12/958622 [patent_app_country] => US [patent_app_date] => 2010-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 14967 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20110134705.pdf [firstpage_image] =>[orig_patent_app_number] => 12958622 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/958622
Integrated circuit package with multiple dies and a multiplexed communications interface Dec 1, 2010 Issued
Array ( [id] => 9312416 [patent_doc_number] => 08653638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Integrated circuit package with multiple dies and bundling of control signals' [patent_app_type] => utility [patent_app_number] => 12/958646 [patent_app_country] => US [patent_app_date] => 2010-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 14450 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12958646 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/958646
Integrated circuit package with multiple dies and bundling of control signals Dec 1, 2010 Issued
Array ( [id] => 9245973 [patent_doc_number] => 08610258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => 'Integrated circuit package with multiple dies and sampled control signals' [patent_app_type] => utility [patent_app_number] => 12/958639 [patent_app_country] => US [patent_app_date] => 2010-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 14441 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12958639 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/958639
Integrated circuit package with multiple dies and sampled control signals Dec 1, 2010 Issued
Array ( [id] => 9274034 [patent_doc_number] => 08637968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-28 [patent_title] => 'Stacked microelectronic assembly having interposer connecting active chips' [patent_app_type] => utility [patent_app_number] => 12/958866 [patent_app_country] => US [patent_app_date] => 2010-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 5997 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12958866 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/958866
Stacked microelectronic assembly having interposer connecting active chips Dec 1, 2010 Issued
Array ( [id] => 9524673 [patent_doc_number] => 08748949 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-10 [patent_title] => 'Chip package with heavily doped region and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 12/940607 [patent_app_country] => US [patent_app_date] => 2010-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 4147 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12940607 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/940607
Chip package with heavily doped region and fabrication method thereof Nov 4, 2010 Issued
Array ( [id] => 9009237 [patent_doc_number] => 08524533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Room temperature metal direct bonding' [patent_app_type] => utility [patent_app_number] => 12/913385 [patent_app_country] => US [patent_app_date] => 2010-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 9118 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12913385 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/913385
Room temperature metal direct bonding Oct 26, 2010 Issued
Array ( [id] => 9009237 [patent_doc_number] => 08524533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Room temperature metal direct bonding' [patent_app_type] => utility [patent_app_number] => 12/913385 [patent_app_country] => US [patent_app_date] => 2010-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 9118 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12913385 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/913385
Room temperature metal direct bonding Oct 26, 2010 Issued
Array ( [id] => 9009237 [patent_doc_number] => 08524533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Room temperature metal direct bonding' [patent_app_type] => utility [patent_app_number] => 12/913385 [patent_app_country] => US [patent_app_date] => 2010-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 9118 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12913385 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/913385
Room temperature metal direct bonding Oct 26, 2010 Issued
Array ( [id] => 9009237 [patent_doc_number] => 08524533 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Room temperature metal direct bonding' [patent_app_type] => utility [patent_app_number] => 12/913385 [patent_app_country] => US [patent_app_date] => 2010-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 9118 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12913385 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/913385
Room temperature metal direct bonding Oct 26, 2010 Issued
Array ( [id] => 8049667 [patent_doc_number] => 20120074568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'METHOD AND SYSTEM FOR MINIMIZING CARRIER STRESS OF A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/890722 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3100 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20120074568.pdf [firstpage_image] =>[orig_patent_app_number] => 12890722 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/890722
Method and system for minimizing carrier stress of a semiconductor device Sep 26, 2010 Issued
Array ( [id] => 9100084 [patent_doc_number] => 08563963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Light-emitting diode die packages and methods for producing same' [patent_app_type] => utility [patent_app_number] => 12/890979 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 2188 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12890979 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/890979
Light-emitting diode die packages and methods for producing same Sep 26, 2010 Issued
Array ( [id] => 9627177 [patent_doc_number] => 08796863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Semiconductor memory devices and semiconductor packages' [patent_app_type] => utility [patent_app_number] => 12/891141 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 34 [patent_no_of_words] => 10821 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12891141 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/891141
Semiconductor memory devices and semiconductor packages Sep 26, 2010 Issued
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