
James M. Mitchell
Supervisory Patent Examiner (ID: 10382, Phone: (571)272-1931 , Office: P/4100 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813, 2827, 4100, 2822, 4127 |
| Total Applications | 769 |
| Issued Applications | 540 |
| Pending Applications | 13 |
| Abandoned Applications | 218 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8897242
[patent_doc_number] => 08476765
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-07-02
[patent_title] => 'Copper interconnect structure having a graphene cap'
[patent_app_type] => utility
[patent_app_number] => 12/961251
[patent_app_country] => US
[patent_app_date] => 2010-12-06
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 2887
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12961251
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/961251 | Copper interconnect structure having a graphene cap | Dec 5, 2010 | Issued |
Array
(
[id] => 7480148
[patent_doc_number] => 20110248399
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-10-13
[patent_title] => 'Semiconductor Device and Method of Forming High Routing Density Interconnect Sites on Substrate'
[patent_app_type] => utility
[patent_app_number] => 12/961027
[patent_app_country] => US
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[pdf_file] => publications/A1/0248/20110248399.pdf
[firstpage_image] =>[orig_patent_app_number] => 12961027
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/961027 | Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate | Dec 5, 2010 | Issued |
Array
(
[id] => 7738927
[patent_doc_number] => 20120018885
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-01-26
[patent_title] => 'SEMICONDUCTOR APPARATUS HAVING THROUGH VIAS'
[patent_app_type] => utility
[patent_app_number] => 12/960843
[patent_app_country] => US
[patent_app_date] => 2010-12-06
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[pdf_file] => publications/A1/0018/20120018885.pdf
[firstpage_image] =>[orig_patent_app_number] => 12960843
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/960843 | Semiconductor apparatus having through vias configured to isolate power supplied to a memory chip from data signals supplied to the memory chip | Dec 5, 2010 | Issued |
Array
(
[id] => 8643201
[patent_doc_number] => 08368189
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-05
[patent_title] => 'Auxiliary leadframe member for stabilizing the bond wire process'
[patent_app_type] => utility
[patent_app_number] => 12/960268
[patent_app_country] => US
[patent_app_date] => 2010-12-03
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/960268 | Auxiliary leadframe member for stabilizing the bond wire process | Dec 2, 2010 | Issued |
Array
(
[id] => 5955888
[patent_doc_number] => 20110180916
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[patent_kind] => A1
[patent_issue_date] => 2011-07-28
[patent_title] => 'MULTI-CHIP PACKAGE HAVING FRAME INTERPOSER'
[patent_app_type] => utility
[patent_app_number] => 12/959596
[patent_app_country] => US
[patent_app_date] => 2010-12-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/959596 | Multi-chip package having frame interposer | Dec 2, 2010 | Issued |
Array
(
[id] => 9882412
[patent_doc_number] => 08969176
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-03-03
[patent_title] => 'Laminated transferable interconnect for microelectronic package'
[patent_app_type] => utility
[patent_app_number] => 12/959549
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/959549 | Laminated transferable interconnect for microelectronic package | Dec 2, 2010 | Issued |
Array
(
[id] => 9086203
[patent_doc_number] => 08557629
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[patent_kind] => B1
[patent_issue_date] => 2013-10-15
[patent_title] => 'Semiconductor device having overlapped via apertures'
[patent_app_type] => utility
[patent_app_number] => 12/959911
[patent_app_country] => US
[patent_app_date] => 2010-12-03
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/959911 | Semiconductor device having overlapped via apertures | Dec 2, 2010 | Issued |
Array
(
[id] => 8224914
[patent_doc_number] => 20120139112
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-07
[patent_title] => 'Selective Seed Layer Treatment for Feature Plating'
[patent_app_type] => utility
[patent_app_number] => 12/958638
[patent_app_country] => US
[patent_app_date] => 2010-12-02
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/958638 | Selective seed layer treatment for feature plating | Dec 1, 2010 | Issued |
Array
(
[id] => 6210858
[patent_doc_number] => 20110134705
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[patent_issue_date] => 2011-06-09
[patent_title] => 'INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND A MULTIPLEXED COMMUNICATIONS INTERFACE'
[patent_app_type] => utility
[patent_app_number] => 12/958622
[patent_app_country] => US
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[pdf_file] => publications/A1/0134/20110134705.pdf
[firstpage_image] =>[orig_patent_app_number] => 12958622
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/958622 | Integrated circuit package with multiple dies and a multiplexed communications interface | Dec 1, 2010 | Issued |
Array
(
[id] => 9312416
[patent_doc_number] => 08653638
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[patent_kind] => B2
[patent_issue_date] => 2014-02-18
[patent_title] => 'Integrated circuit package with multiple dies and bundling of control signals'
[patent_app_type] => utility
[patent_app_number] => 12/958646
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Array
(
[id] => 9245973
[patent_doc_number] => 08610258
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[patent_issue_date] => 2013-12-17
[patent_title] => 'Integrated circuit package with multiple dies and sampled control signals'
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Array
(
[id] => 9274034
[patent_doc_number] => 08637968
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[patent_issue_date] => 2014-01-28
[patent_title] => 'Stacked microelectronic assembly having interposer connecting active chips'
[patent_app_type] => utility
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Array
(
[id] => 9524673
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[patent_issue_date] => 2014-06-10
[patent_title] => 'Chip package with heavily doped region and fabrication method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/940607 | Chip package with heavily doped region and fabrication method thereof | Nov 4, 2010 | Issued |
Array
(
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Array
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Array
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Array
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Array
(
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/891141 | Semiconductor memory devices and semiconductor packages | Sep 26, 2010 | Issued |