Search

James M. Mitchell

Supervisory Patent Examiner (ID: 10382, Phone: (571)272-1931 , Office: P/4100 )

Most Active Art Unit
2813
Art Unit(s)
2813, 2827, 4100, 2822, 4127
Total Applications
769
Issued Applications
540
Pending Applications
13
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6114690 [patent_doc_number] => 20110074050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'FILM FOR SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/890909 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 15280 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20110074050.pdf [firstpage_image] =>[orig_patent_app_number] => 12890909 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/890909
FILM FOR SEMICONDUCTOR DEVICE Sep 26, 2010 Abandoned
Array ( [id] => 9250725 [patent_doc_number] => 08614507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-24 [patent_title] => 'Semiconductor devices having lower and upper interconnection structures that exhibit reduced coupling' [patent_app_type] => utility [patent_app_number] => 12/889499 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 6292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12889499 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/889499
Semiconductor devices having lower and upper interconnection structures that exhibit reduced coupling Sep 23, 2010 Issued
Array ( [id] => 7738925 [patent_doc_number] => 20120018884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'Semiconductor package structure and forming method thereof' [patent_app_type] => utility [patent_app_number] => 12/923461 [patent_app_country] => US [patent_app_date] => 2010-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2162 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20120018884.pdf [firstpage_image] =>[orig_patent_app_number] => 12923461 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/923461
Semiconductor package structure and forming method thereof Sep 22, 2010 Abandoned
Array ( [id] => 9047338 [patent_doc_number] => 08541892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-24 [patent_title] => 'Bonding connection between a bonding wire and a power semiconductor chip' [patent_app_type] => utility [patent_app_number] => 12/888781 [patent_app_country] => US [patent_app_date] => 2010-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12888781 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/888781
Bonding connection between a bonding wire and a power semiconductor chip Sep 22, 2010 Issued
Array ( [id] => 9582949 [patent_doc_number] => 08772952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-08 [patent_title] => 'Semiconductor device with copper wire having different width portions' [patent_app_type] => utility [patent_app_number] => 12/889023 [patent_app_country] => US [patent_app_date] => 2010-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 12006 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12889023 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/889023
Semiconductor device with copper wire having different width portions Sep 22, 2010 Issued
Array ( [id] => 7762805 [patent_doc_number] => 20120032328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'Package structure with underfilling material and packaging method thereof' [patent_app_type] => utility [patent_app_number] => 12/923462 [patent_app_country] => US [patent_app_date] => 2010-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20120032328.pdf [firstpage_image] =>[orig_patent_app_number] => 12923462 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/923462
Package structure with underfilling material and packaging method thereof Sep 22, 2010 Abandoned
Array ( [id] => 6130799 [patent_doc_number] => 20110006438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE FORMED THEREFROM' [patent_app_type] => utility [patent_app_number] => 12/887798 [patent_app_country] => US [patent_app_date] => 2010-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4959 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20110006438.pdf [firstpage_image] =>[orig_patent_app_number] => 12887798 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/887798
Semiconductor wafer, and semiconductor device formed therefrom Sep 21, 2010 Issued
Array ( [id] => 7550637 [patent_doc_number] => 08062969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Methods of selectively growing nickel-containing materials' [patent_app_type] => utility [patent_app_number] => 12/885827 [patent_app_country] => US [patent_app_date] => 2010-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3427 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/062/08062969.pdf [firstpage_image] =>[orig_patent_app_number] => 12885827 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/885827
Methods of selectively growing nickel-containing materials Sep 19, 2010 Issued
Array ( [id] => 8028175 [patent_doc_number] => 08143169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Methods for multi-stage molding of integrated circuit package' [patent_app_type] => utility [patent_app_number] => 12/878134 [patent_app_country] => US [patent_app_date] => 2010-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2941 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/143/08143169.pdf [firstpage_image] =>[orig_patent_app_number] => 12878134 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/878134
Methods for multi-stage molding of integrated circuit package Sep 8, 2010 Issued
Array ( [id] => 6609771 [patent_doc_number] => 20100323479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'Semiconductor Component with Surface Mountable Devices and Method for Producing the Same' [patent_app_type] => utility [patent_app_number] => 12/868422 [patent_app_country] => US [patent_app_date] => 2010-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2015 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0323/20100323479.pdf [firstpage_image] =>[orig_patent_app_number] => 12868422 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/868422
Semiconductor component with surface mountable devices and method for producing the same Aug 24, 2010 Issued
Array ( [id] => 6586184 [patent_doc_number] => 20100308460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'Method of Ball Grid Array Package Construction with Raised Solder Ball Pads' [patent_app_type] => utility [patent_app_number] => 12/857832 [patent_app_country] => US [patent_app_date] => 2010-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4426 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0308/20100308460.pdf [firstpage_image] =>[orig_patent_app_number] => 12857832 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/857832
Method of ball grid array package construction with raised solder ball pads Aug 16, 2010 Issued
Array ( [id] => 9413532 [patent_doc_number] => 08697569 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Non-lithographic formation of three-dimensional conductive elements' [patent_app_type] => utility [patent_app_number] => 12/842669 [patent_app_country] => US [patent_app_date] => 2010-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 8824 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12842669 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/842669
Non-lithographic formation of three-dimensional conductive elements Jul 22, 2010 Issued
Array ( [id] => 7743466 [patent_doc_number] => 20120021565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-26 [patent_title] => 'METHOD OF FORMING A PACKAGED SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/842562 [patent_app_country] => US [patent_app_date] => 2010-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20120021565.pdf [firstpage_image] =>[orig_patent_app_number] => 12842562 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/842562
Method of forming a packaged semiconductor device Jul 22, 2010 Issued
Array ( [id] => 6489026 [patent_doc_number] => 20100285654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING REDUCED DIE-WARPAGE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/839573 [patent_app_country] => US [patent_app_date] => 2010-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6625 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20100285654.pdf [firstpage_image] =>[orig_patent_app_number] => 12839573 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/839573
SEMICONDUCTOR DEVICE HAVING REDUCED DIE-WARPAGE AND METHOD OF MANUFACTURING THE SAME Jul 19, 2010 Abandoned
Array ( [id] => 6231331 [patent_doc_number] => 20100264529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTEGRAL INNER LEAD AND PADDLE AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 12/823079 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20100264529.pdf [firstpage_image] =>[orig_patent_app_number] => 12823079 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/823079
Integrated circuit package system with integral inner lead and paddle and method of manufacture thereof Jun 23, 2010 Issued
Array ( [id] => 7564951 [patent_doc_number] => 20110285014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'PACKAGING STRUCTURE AND PACKAGE PROCESS' [patent_app_type] => utility [patent_app_number] => 12/817396 [patent_app_country] => US [patent_app_date] => 2010-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20110285014.pdf [firstpage_image] =>[orig_patent_app_number] => 12817396 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/817396
Package process Jun 16, 2010 Issued
Array ( [id] => 6369026 [patent_doc_number] => 20100314728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'IC PACKAGE HAVING AN INDUCTOR ETCHED INTO A LEADFRAME THEREOF' [patent_app_type] => utility [patent_app_number] => 12/816974 [patent_app_country] => US [patent_app_date] => 2010-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3174 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0314/20100314728.pdf [firstpage_image] =>[orig_patent_app_number] => 12816974 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/816974
IC PACKAGE HAVING AN INDUCTOR ETCHED INTO A LEADFRAME THEREOF Jun 15, 2010 Abandoned
Array ( [id] => 6375102 [patent_doc_number] => 20100301333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF INSPECTING AN ELECTRICAL CHARACTERISTIC OF A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/787815 [patent_app_country] => US [patent_app_date] => 2010-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4083 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20100301333.pdf [firstpage_image] =>[orig_patent_app_number] => 12787815 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787815
SEMICONDUCTOR DEVICE AND METHOD OF INSPECTING AN ELECTRICAL CHARACTERISTIC OF A SEMICONDUCTOR DEVICE May 25, 2010 Abandoned
Array ( [id] => 6328183 [patent_doc_number] => 20100327453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'Semiconductor Device and Method of Manufacturing the Same' [patent_app_type] => utility [patent_app_number] => 12/787880 [patent_app_country] => US [patent_app_date] => 2010-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6555 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20100327453.pdf [firstpage_image] =>[orig_patent_app_number] => 12787880 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787880
Semiconductor Device and Method of Manufacturing the Same May 25, 2010 Abandoned
Array ( [id] => 9154190 [patent_doc_number] => 08587097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Semiconductor device that suppresses malfunctions due to noise generated in internal circuit' [patent_app_type] => utility [patent_app_number] => 12/787873 [patent_app_country] => US [patent_app_date] => 2010-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3685 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12787873 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787873
Semiconductor device that suppresses malfunctions due to noise generated in internal circuit May 25, 2010 Issued
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