
James M. Mitchell
Supervisory Patent Examiner (ID: 10382, Phone: (571)272-1931 , Office: P/4100 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813, 2827, 4100, 2822, 4127 |
| Total Applications | 769 |
| Issued Applications | 540 |
| Pending Applications | 13 |
| Abandoned Applications | 218 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6114690
[patent_doc_number] => 20110074050
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-03-31
[patent_title] => 'FILM FOR SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/890909
[patent_app_country] => US
[patent_app_date] => 2010-09-27
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[pdf_file] => publications/A1/0074/20110074050.pdf
[firstpage_image] =>[orig_patent_app_number] => 12890909
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/890909 | FILM FOR SEMICONDUCTOR DEVICE | Sep 26, 2010 | Abandoned |
Array
(
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[patent_doc_number] => 08614507
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[patent_kind] => B2
[patent_issue_date] => 2013-12-24
[patent_title] => 'Semiconductor devices having lower and upper interconnection structures that exhibit reduced coupling'
[patent_app_type] => utility
[patent_app_number] => 12/889499
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[patent_app_date] => 2010-09-24
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/889499 | Semiconductor devices having lower and upper interconnection structures that exhibit reduced coupling | Sep 23, 2010 | Issued |
Array
(
[id] => 7738925
[patent_doc_number] => 20120018884
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[patent_kind] => A1
[patent_issue_date] => 2012-01-26
[patent_title] => 'Semiconductor package structure and forming method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/923461
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Array
(
[id] => 9047338
[patent_doc_number] => 08541892
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[patent_kind] => B2
[patent_issue_date] => 2013-09-24
[patent_title] => 'Bonding connection between a bonding wire and a power semiconductor chip'
[patent_app_type] => utility
[patent_app_number] => 12/888781
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[patent_app_date] => 2010-09-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/888781 | Bonding connection between a bonding wire and a power semiconductor chip | Sep 22, 2010 | Issued |
Array
(
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[patent_issue_date] => 2014-07-08
[patent_title] => 'Semiconductor device with copper wire having different width portions'
[patent_app_type] => utility
[patent_app_number] => 12/889023
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/889023 | Semiconductor device with copper wire having different width portions | Sep 22, 2010 | Issued |
Array
(
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[patent_issue_date] => 2012-02-09
[patent_title] => 'Package structure with underfilling material and packaging method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/923462
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Array
(
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[patent_doc_number] => 20110006438
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[patent_kind] => A1
[patent_issue_date] => 2011-01-13
[patent_title] => 'SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE FORMED THEREFROM'
[patent_app_type] => utility
[patent_app_number] => 12/887798
[patent_app_country] => US
[patent_app_date] => 2010-09-22
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[pdf_file] => publications/A1/0006/20110006438.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/887798 | Semiconductor wafer, and semiconductor device formed therefrom | Sep 21, 2010 | Issued |
Array
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[id] => 7550637
[patent_doc_number] => 08062969
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[patent_issue_date] => 2011-11-22
[patent_title] => 'Methods of selectively growing nickel-containing materials'
[patent_app_type] => utility
[patent_app_number] => 12/885827
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/885827 | Methods of selectively growing nickel-containing materials | Sep 19, 2010 | Issued |
Array
(
[id] => 8028175
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/878134 | Methods for multi-stage molding of integrated circuit package | Sep 8, 2010 | Issued |
Array
(
[id] => 6609771
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[patent_issue_date] => 2010-12-23
[patent_title] => 'Semiconductor Component with Surface Mountable Devices and Method for Producing the Same'
[patent_app_type] => utility
[patent_app_number] => 12/868422
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/868422 | Semiconductor component with surface mountable devices and method for producing the same | Aug 24, 2010 | Issued |
Array
(
[id] => 6586184
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[patent_title] => 'Method of Ball Grid Array Package Construction with Raised Solder Ball Pads'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/857832 | Method of ball grid array package construction with raised solder ball pads | Aug 16, 2010 | Issued |
Array
(
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Array
(
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Array
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Array
(
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[patent_doc_number] => 20100264529
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/823079 | Integrated circuit package system with integral inner lead and paddle and method of manufacture thereof | Jun 23, 2010 | Issued |
Array
(
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Array
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Array
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Array
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Array
(
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[patent_title] => 'Semiconductor device that suppresses malfunctions due to noise generated in internal circuit'
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[patent_app_number] => 12/787873
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/787873 | Semiconductor device that suppresses malfunctions due to noise generated in internal circuit | May 25, 2010 | Issued |