Search

James M. Mitchell

Supervisory Patent Examiner (ID: 10382, Phone: (571)272-1931 , Office: P/4100 )

Most Active Art Unit
2813
Art Unit(s)
2813, 2827, 4100, 2822, 4127
Total Applications
769
Issued Applications
540
Pending Applications
13
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9245252 [patent_doc_number] => 08609532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => 'Magnetically sintered conductive via' [patent_app_type] => utility [patent_app_number] => 12/787968 [patent_app_country] => US [patent_app_date] => 2010-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3861 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12787968 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787968
Magnetically sintered conductive via May 25, 2010 Issued
Array ( [id] => 8944352 [patent_doc_number] => 08497534 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-30 [patent_title] => 'Chip package with heavily doped regions and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 12/788091 [patent_app_country] => US [patent_app_date] => 2010-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 4115 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12788091 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/788091
Chip package with heavily doped regions and fabrication method thereof May 25, 2010 Issued
Array ( [id] => 6376003 [patent_doc_number] => 20100301468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/787770 [patent_app_country] => US [patent_app_date] => 2010-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8056 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20100301468.pdf [firstpage_image] =>[orig_patent_app_number] => 12787770 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787770
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME May 25, 2010 Abandoned
Array ( [id] => 7577367 [patent_doc_number] => 20110291249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'Semiconductor Device and Method of Forming Conductive Posts and Heat Sink Over Semiconductor Die Using Leadframe' [patent_app_type] => utility [patent_app_number] => 12/787973 [patent_app_country] => US [patent_app_date] => 2010-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5544 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20110291249.pdf [firstpage_image] =>[orig_patent_app_number] => 12787973 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787973
Semiconductor device and method of forming conductive posts and heat sink over semiconductor die using leadframe May 25, 2010 Issued
Array ( [id] => 9127802 [patent_doc_number] => 08575753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'Semiconductor device having a conductive structure including oxide and non oxide portions' [patent_app_type] => utility [patent_app_number] => 12/787056 [patent_app_country] => US [patent_app_date] => 2010-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 68 [patent_no_of_words] => 29663 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12787056 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787056
Semiconductor device having a conductive structure including oxide and non oxide portions May 24, 2010 Issued
Array ( [id] => 8846121 [patent_doc_number] => 08455300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Integrated circuit package system with embedded die superstructure and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 12/787216 [patent_app_country] => US [patent_app_date] => 2010-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6222 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12787216 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787216
Integrated circuit package system with embedded die superstructure and method of manufacture thereof May 24, 2010 Issued
Array ( [id] => 7987739 [patent_doc_number] => 08076164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-13 [patent_title] => 'On-die bond wires system and method for enhancing routability of a redistribution layer' [patent_app_type] => utility [patent_app_number] => 12/774634 [patent_app_country] => US [patent_app_date] => 2010-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4926 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/076/08076164.pdf [firstpage_image] =>[orig_patent_app_number] => 12774634 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/774634
On-die bond wires system and method for enhancing routability of a redistribution layer May 4, 2010 Issued
Array ( [id] => 8543248 [patent_doc_number] => 08318537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Flip chip interconnection having narrow interconnection sites on the substrate' [patent_app_type] => utility [patent_app_number] => 12/757889 [patent_app_country] => US [patent_app_date] => 2010-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 30 [patent_no_of_words] => 9333 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12757889 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/757889
Flip chip interconnection having narrow interconnection sites on the substrate Apr 8, 2010 Issued
Array ( [id] => 8543248 [patent_doc_number] => 08318537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Flip chip interconnection having narrow interconnection sites on the substrate' [patent_app_type] => utility [patent_app_number] => 12/757889 [patent_app_country] => US [patent_app_date] => 2010-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 30 [patent_no_of_words] => 9333 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12757889 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/757889
Flip chip interconnection having narrow interconnection sites on the substrate Apr 8, 2010 Issued
Array ( [id] => 8909828 [patent_doc_number] => 08481892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-09 [patent_title] => 'Ceramic heater and method for producing same' [patent_app_type] => utility [patent_app_number] => 12/732449 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6150 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12732449 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/732449
Ceramic heater and method for producing same Mar 25, 2010 Issued
Array ( [id] => 8306302 [patent_doc_number] => 08227839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-24 [patent_title] => 'Integrated circuit having TSVS including hillock suppression' [patent_app_type] => utility [patent_app_number] => 12/726057 [patent_app_country] => US [patent_app_date] => 2010-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4113 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12726057 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/726057
Integrated circuit having TSVS including hillock suppression Mar 16, 2010 Issued
Array ( [id] => 7699379 [patent_doc_number] => 20110227211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE LEADS AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 12/726342 [patent_app_country] => US [patent_app_date] => 2010-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20110227211.pdf [firstpage_image] =>[orig_patent_app_number] => 12726342 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/726342
Integrated circuit packaging system with bump contact on package leads and method of manufacture thereof Mar 16, 2010 Issued
Array ( [id] => 7699371 [patent_doc_number] => 20110227219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'ENHANCED WLP FOR SUPERIOR TEMP CYCLING, DROP TEST AND HIGH CURRENT APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 12/725967 [patent_app_country] => US [patent_app_date] => 2010-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20110227219.pdf [firstpage_image] =>[orig_patent_app_number] => 12725967 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/725967
Enhanced WLP for superior temp cycling, drop test and high current applications Mar 16, 2010 Issued
Array ( [id] => 8760715 [patent_doc_number] => 08421239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Crenulated wiring structure and method for integrated circuit interconnects' [patent_app_type] => utility [patent_app_number] => 12/724903 [patent_app_country] => US [patent_app_date] => 2010-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3268 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12724903 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/724903
Crenulated wiring structure and method for integrated circuit interconnects Mar 15, 2010 Issued
Array ( [id] => 6369275 [patent_doc_number] => 20100314771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING AN IMPROVED LITHOGRAPHIC MARGIN' [patent_app_type] => utility [patent_app_number] => 12/724051 [patent_app_country] => US [patent_app_date] => 2010-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4134 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0314/20100314771.pdf [firstpage_image] =>[orig_patent_app_number] => 12724051 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/724051
SEMICONDUCTOR DEVICE INCLUDING AN IMPROVED LITHOGRAPHIC MARGIN Mar 14, 2010 Abandoned
Array ( [id] => 6010657 [patent_doc_number] => 20110221054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'Semiconductor Device and Method of Forming Conductive Vias Through Interconnect Structures and Encapsulant of WLCSP' [patent_app_type] => utility [patent_app_number] => 12/724354 [patent_app_country] => US [patent_app_date] => 2010-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5748 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20110221054.pdf [firstpage_image] =>[orig_patent_app_number] => 12724354 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/724354
Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSP Mar 14, 2010 Issued
Array ( [id] => 6519070 [patent_doc_number] => 20100230795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'STACKED MICROELECTRONIC ASSEMBLIES HAVING VIAS EXTENDING THROUGH BOND PADS' [patent_app_type] => utility [patent_app_number] => 12/723039 [patent_app_country] => US [patent_app_date] => 2010-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 14418 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20100230795.pdf [firstpage_image] =>[orig_patent_app_number] => 12723039 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/723039
Stacked microelectronic assemblies having vias extending through bond pads Mar 11, 2010 Issued
Array ( [id] => 6519287 [patent_doc_number] => 20100230811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING A CONDUCTIVE BUMP' [patent_app_type] => utility [patent_app_number] => 12/722794 [patent_app_country] => US [patent_app_date] => 2010-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 9474 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20100230811.pdf [firstpage_image] =>[orig_patent_app_number] => 12722794 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/722794
Semiconductor device having a conductive bump Mar 11, 2010 Issued
Array ( [id] => 8458583 [patent_doc_number] => 08294253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Semiconductor device, electronic device and method of manufacturing semiconductor device, having electronic component, sealing resin and multilayer wiring structure' [patent_app_type] => utility [patent_app_number] => 12/722769 [patent_app_country] => US [patent_app_date] => 2010-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9624 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12722769 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/722769
Semiconductor device, electronic device and method of manufacturing semiconductor device, having electronic component, sealing resin and multilayer wiring structure Mar 11, 2010 Issued
Array ( [id] => 6376034 [patent_doc_number] => 20100301472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'ELECTRONIC COMPONENT AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/721741 [patent_app_country] => US [patent_app_date] => 2010-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5460 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20100301472.pdf [firstpage_image] =>[orig_patent_app_number] => 12721741 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/721741
Electronic component and method of connecting with multi-profile bumps Mar 10, 2010 Issued
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