James M. Mitchell

Array ( [id] => 6264345 [patent_doc_number] => 20100252939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'CHIP MODULE AND METHOD FOR PRODUCING A CHIP MODULE' [patent_app_type] => utility [patent_app_number] => 12/721785 [patent_app_country] => US [patent_app_date] => 2010-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2952 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20100252939.pdf [firstpage_image] =>[orig_patent_app_number] => 12721785 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6286310 [patent_doc_number] => 20100237508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'POWER-SUPPLY WIRING STRUCTURE FOR MULTILAYER WIRING AND METHOD OF MANUFACTURING MULTILAYER WIRING' [patent_app_type] => utility [patent_app_number] => 12/721734 [patent_app_country] => US [patent_app_date] => 2010-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8291 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20100237508.pdf [firstpage_image] =>[orig_patent_app_number] => 12721734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9047332 [patent_doc_number] => 08541886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-24 [patent_title] => 'Integrated circuit packaging system with via and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 12/720667 [patent_app_country] => US [patent_app_date] => 2010-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7497 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12720667 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6393467 [patent_doc_number] => 20100164107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING MULTILAYERED INTERCONNECTION STRUCTURE FORMED BY USING Cu DAMASCENE METHOD, AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/719653 [patent_app_country] => US [patent_app_date] => 2010-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6386 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20100164107.pdf [firstpage_image] =>[orig_patent_app_number] => 12719653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6478979 [patent_doc_number] => 20100213589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'MULTI-CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/704517 [patent_app_country] => US [patent_app_date] => 2010-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8403 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20100213589.pdf [firstpage_image] =>[orig_patent_app_number] => 12704517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6438883 [patent_doc_number] => 20100144139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'Methods For Fabricating Semiconductor Components With Conductive Interconnects Having Planar Surfaces' [patent_app_type] => utility [patent_app_number] => 12/703520 [patent_app_country] => US [patent_app_date] => 2010-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 12621 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20100144139.pdf [firstpage_image] =>[orig_patent_app_number] => 12703520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9245753 [patent_doc_number] => 08610035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => 'Drawer type cooking device' [patent_app_type] => utility [patent_app_number] => 12/700318 [patent_app_country] => US [patent_app_date] => 2010-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6095 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12700318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6193130 [patent_doc_number] => 20110024884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'Structure of Mixed Semiconductor Encapsulation Structure with Multiple Chips and Capacitors' [patent_app_type] => utility [patent_app_number] => 12/693446 [patent_app_country] => US [patent_app_date] => 2010-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20110024884.pdf [firstpage_image] =>[orig_patent_app_number] => 12693446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8772893 [patent_doc_number] => 08426851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-23 [patent_title] => 'Thin film transistor and display device' [patent_app_type] => utility [patent_app_number] => 12/654658 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 7427 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12654658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6293040 [patent_doc_number] => 20100159644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'LOW-COST FLIP-CHIP INTERCONNECT WITH AN INTEGRATED WAFER-APPLIED PHOTO-SENSITIVE ADHESIVE AND METAL-LOADED EPOXY PASTE SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/642445 [patent_app_country] => US [patent_app_date] => 2009-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4665 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20100159644.pdf [firstpage_image] =>[orig_patent_app_number] => 12642445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9355737 [patent_doc_number] => 08674270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Cooking appliance with programmable recipe system' [patent_app_type] => utility [patent_app_number] => 12/641427 [patent_app_country] => US [patent_app_date] => 2009-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3611 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12641427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6349151 [patent_doc_number] => 20100071941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'DIELECTRIC SPACERS FOR METAL INTERCONNECTS AND METHOD TO FORM THE SAME' [patent_app_type] => utility [patent_app_number] => 12/630771 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4838 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20100071941.pdf [firstpage_image] =>[orig_patent_app_number] => 12630771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8533242 [patent_doc_number] => 08309396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'System and method for 3D integrated circuit stacking' [patent_app_type] => utility [patent_app_number] => 12/616920 [patent_app_country] => US [patent_app_date] => 2009-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2069 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12616920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6272301 [patent_doc_number] => 20100117241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME' [patent_app_type] => utility [patent_app_number] => 12/615449 [patent_app_country] => US [patent_app_date] => 2009-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15532 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20100117241.pdf [firstpage_image] =>[orig_patent_app_number] => 12615449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7801573 [patent_doc_number] => 08129847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Interconnect and method for mounting an electronic device to a substrate' [patent_app_type] => utility [patent_app_number] => 12/615321 [patent_app_country] => US [patent_app_date] => 2009-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1512 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/129/08129847.pdf [firstpage_image] =>[orig_patent_app_number] => 12615321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9350606 [patent_doc_number] => 08669498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-11 [patent_title] => 'Cooker' [patent_app_type] => utility [patent_app_number] => 12/585695 [patent_app_country] => US [patent_app_date] => 2009-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6816 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12585695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10870163 [patent_doc_number] => 08895358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Semiconductor device and method of forming cavity in PCB containing encapsulant or dummy die having CTE similar to CTE of large array WLCSP' [patent_app_type] => utility [patent_app_number] => 12/557763 [patent_app_country] => US [patent_app_date] => 2009-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5321 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12557763 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6231338 [patent_doc_number] => 20100264534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/542154 [patent_app_country] => US [patent_app_date] => 2009-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4106 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20100264534.pdf [firstpage_image] =>[orig_patent_app_number] => 12542154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6216104 [patent_doc_number] => 20100052148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'PACKAGE STRUCTURE AND PACKAGE SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/541253 [patent_app_country] => US [patent_app_date] => 2009-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5055 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20100052148.pdf [firstpage_image] =>[orig_patent_app_number] => 12541253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8435425 [patent_doc_number] => 08283193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'Integrated circuit system with sealring and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 12/541373 [patent_app_country] => US [patent_app_date] => 2009-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12541373 [rel_patent_id] =>[rel_patent_doc_number] =>)