
James M. Mitchell
Supervisory Patent Examiner (ID: 10382, Phone: (571)272-1931 , Office: P/4100 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813, 2827, 4100, 2822, 4127 |
| Total Applications | 769 |
| Issued Applications | 540 |
| Pending Applications | 13 |
| Abandoned Applications | 218 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4624200
[patent_doc_number] => 08003496
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-23
[patent_title] => 'Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die'
[patent_app_type] => utility
[patent_app_number] => 12/541334
[patent_app_country] => US
[patent_app_date] => 2009-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 16
[patent_no_of_words] => 4026
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/003/08003496.pdf
[firstpage_image] =>[orig_patent_app_number] => 12541334
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/541334 | Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die | Aug 13, 2009 | Issued |
Array
(
[id] => 8435425
[patent_doc_number] => 08283193
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-10-09
[patent_title] => 'Integrated circuit system with sealring and method of manufacture thereof'
[patent_app_type] => utility
[patent_app_number] => 12/541373
[patent_app_country] => US
[patent_app_date] => 2009-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 5377
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12541373
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/541373 | Integrated circuit system with sealring and method of manufacture thereof | Aug 13, 2009 | Issued |
Array
(
[id] => 6458485
[patent_doc_number] => 20100090344
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-15
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/540043
[patent_app_country] => US
[patent_app_date] => 2009-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6905
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0090/20100090344.pdf
[firstpage_image] =>[orig_patent_app_number] => 12540043
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/540043 | Semiconductor device | Aug 11, 2009 | Issued |
Array
(
[id] => 5948496
[patent_doc_number] => 20110031603
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-10
[patent_title] => 'SEMICONDUCTOR DEVICES HAVING STRESS RELIEF LAYERS AND METHODS FOR FABRICATING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/538293
[patent_app_country] => US
[patent_app_date] => 2009-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5897
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0031/20110031603.pdf
[firstpage_image] =>[orig_patent_app_number] => 12538293
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/538293 | Semiconductor devices having stress relief layers and methods for fabricating the same | Aug 9, 2009 | Issued |
Array
(
[id] => 8147194
[patent_doc_number] => 08164199
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-04-24
[patent_title] => 'Multi-die package'
[patent_app_type] => utility
[patent_app_number] => 12/534057
[patent_app_country] => US
[patent_app_date] => 2009-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2616
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/164/08164199.pdf
[firstpage_image] =>[orig_patent_app_number] => 12534057
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/534057 | Multi-die package | Jul 30, 2009 | Issued |
Array
(
[id] => 6193134
[patent_doc_number] => 20110024888
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-03
[patent_title] => 'Semiconductor Device and Method of Mounting Die with TSV in Cavity of Substrate for Electrical Interconnect of FI-POP'
[patent_app_type] => utility
[patent_app_number] => 12/533943
[patent_app_country] => US
[patent_app_date] => 2009-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7755
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20110024888.pdf
[firstpage_image] =>[orig_patent_app_number] => 12533943
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/533943 | Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP | Jul 30, 2009 | Issued |
Array
(
[id] => 4528455
[patent_doc_number] => 07923291
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-12
[patent_title] => 'Method of fabricating electronic device having stacked chips'
[patent_app_type] => utility
[patent_app_number] => 12/458923
[patent_app_country] => US
[patent_app_date] => 2009-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 8731
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/923/07923291.pdf
[firstpage_image] =>[orig_patent_app_number] => 12458923
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/458923 | Method of fabricating electronic device having stacked chips | Jul 27, 2009 | Issued |
Array
(
[id] => 6336125
[patent_doc_number] => 20100019271
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-28
[patent_title] => 'EPOXY RESIN COMPOSITION FOR OPTICAL SEMICONDUCTOR ELEMENT ENCAPSULATION AND OPTICAL SEMICONDUCTOR DEVICE USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/509764
[patent_app_country] => US
[patent_app_date] => 2009-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 6060
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0019/20100019271.pdf
[firstpage_image] =>[orig_patent_app_number] => 12509764
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/509764 | Epoxy resin composition for optical semiconductor element encapsulation and optical semiconductor device using the same | Jul 26, 2009 | Issued |
Array
(
[id] => 8871189
[patent_doc_number] => 08466568
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-06-18
[patent_title] => 'Multi-component device integrated into a matrix'
[patent_app_type] => utility
[patent_app_number] => 12/505385
[patent_app_country] => US
[patent_app_date] => 2009-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 21
[patent_no_of_words] => 5892
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12505385
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/505385 | Multi-component device integrated into a matrix | Jul 16, 2009 | Issued |
Array
(
[id] => 7965731
[patent_doc_number] => 07939381
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-10
[patent_title] => 'Method of semiconductor packaging and/or a semiconductor package'
[patent_app_type] => utility
[patent_app_number] => 12/503604
[patent_app_country] => US
[patent_app_date] => 2009-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 1430
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/939/07939381.pdf
[firstpage_image] =>[orig_patent_app_number] => 12503604
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/503604 | Method of semiconductor packaging and/or a semiconductor package | Jul 14, 2009 | Issued |
Array
(
[id] => 6503076
[patent_doc_number] => 20100013078
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-21
[patent_title] => 'ADHESIVE FOR CONNECTION OF CIRCUIT MEMBER AND SEMICONDUCTOR DEVICE USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/500114
[patent_app_country] => US
[patent_app_date] => 2009-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 14672
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0013/20100013078.pdf
[firstpage_image] =>[orig_patent_app_number] => 12500114
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/500114 | Adhesive for connection of circuit member and semiconductor device using the same | Jul 8, 2009 | Issued |
Array
(
[id] => 6464588
[patent_doc_number] => 20100007035
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-14
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 12/458278
[patent_app_country] => US
[patent_app_date] => 2009-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2646
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0007/20100007035.pdf
[firstpage_image] =>[orig_patent_app_number] => 12458278
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/458278 | Semiconductor device and method of manufacturing the same | Jul 6, 2009 | Issued |
Array
(
[id] => 6464298
[patent_doc_number] => 20100007005
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-14
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/458217
[patent_app_country] => US
[patent_app_date] => 2009-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 6825
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0007/20100007005.pdf
[firstpage_image] =>[orig_patent_app_number] => 12458217
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/458217 | Semiconductor device | Jul 1, 2009 | Abandoned |
Array
(
[id] => 5483324
[patent_doc_number] => 20090273089
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-05
[patent_title] => 'Method for manufacturing semiconductor device and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/458198
[patent_app_country] => US
[patent_app_date] => 2009-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5039
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0273/20090273089.pdf
[firstpage_image] =>[orig_patent_app_number] => 12458198
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/458198 | Method for manufacturing semiconductor device and semiconductor device | Jul 1, 2009 | Issued |
Array
(
[id] => 6328007
[patent_doc_number] => 20100327421
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-30
[patent_title] => 'IC PACKAGE DESIGN WITH STRESS RELIEF FEATURE'
[patent_app_type] => utility
[patent_app_number] => 12/495515
[patent_app_country] => US
[patent_app_date] => 2009-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4744
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0327/20100327421.pdf
[firstpage_image] =>[orig_patent_app_number] => 12495515
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/495515 | IC PACKAGE DESIGN WITH STRESS RELIEF FEATURE | Jun 29, 2009 | Abandoned |
Array
(
[id] => 5461724
[patent_doc_number] => 20090321924
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-31
[patent_title] => 'Power Semiconductor Module'
[patent_app_type] => utility
[patent_app_number] => 12/493629
[patent_app_country] => US
[patent_app_date] => 2009-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5501
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0321/20090321924.pdf
[firstpage_image] =>[orig_patent_app_number] => 12493629
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/493629 | Power Semiconductor Module | Jun 28, 2009 | Abandoned |
Array
(
[id] => 8527721
[patent_doc_number] => 08304291
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-11-06
[patent_title] => 'Semiconductor chip thermal interface structures'
[patent_app_type] => utility
[patent_app_number] => 12/493352
[patent_app_country] => US
[patent_app_date] => 2009-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3754
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12493352
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/493352 | Semiconductor chip thermal interface structures | Jun 28, 2009 | Issued |
Array
(
[id] => 6417338
[patent_doc_number] => 20100276795
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-11-04
[patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/493321
[patent_app_country] => US
[patent_app_date] => 2009-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 6928
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0276/20100276795.pdf
[firstpage_image] =>[orig_patent_app_number] => 12493321
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/493321 | Semiconductor package having through-electrodes which are electrically connected with internal circuit patterns formed in a semiconductor chip and method for manufacturing the same | Jun 28, 2009 | Issued |
Array
(
[id] => 6369115
[patent_doc_number] => 20100314742
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-16
[patent_title] => 'SEMICONDUCTOR PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 12/493290
[patent_app_country] => US
[patent_app_date] => 2009-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5118
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0314/20100314742.pdf
[firstpage_image] =>[orig_patent_app_number] => 12493290
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/493290 | Semiconductor package | Jun 28, 2009 | Issued |
Array
(
[id] => 6614935
[patent_doc_number] => 20100224998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-09-09
[patent_title] => 'Integrated Circuit with Ribtan Interconnects'
[patent_app_type] => utility
[patent_app_number] => 12/492125
[patent_app_country] => US
[patent_app_date] => 2009-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 12556
[patent_no_of_claims] => 44
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0224/20100224998.pdf
[firstpage_image] =>[orig_patent_app_number] => 12492125
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/492125 | Integrated Circuit with Ribtan Interconnects | Jun 24, 2009 | Abandoned |