
James M. Mitchell
Supervisory Patent Examiner (ID: 10382, Phone: (571)272-1931 , Office: P/4100 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813, 2827, 4100, 2822, 4127 |
| Total Applications | 769 |
| Issued Applications | 540 |
| Pending Applications | 13 |
| Abandoned Applications | 218 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8214852
[patent_doc_number] => 08193542
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-06-05
[patent_title] => 'Photoelectric apparatus and imaging apparatus including the same'
[patent_app_type] => utility
[patent_app_number] => 12/490920
[patent_app_country] => US
[patent_app_date] => 2009-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 44
[patent_no_of_words] => 18048
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/193/08193542.pdf
[firstpage_image] =>[orig_patent_app_number] => 12490920
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/490920 | Photoelectric apparatus and imaging apparatus including the same | Jun 23, 2009 | Issued |
Array
(
[id] => 7811696
[patent_doc_number] => 08134228
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-13
[patent_title] => 'Semiconductor device for battery power voltage control'
[patent_app_type] => utility
[patent_app_number] => 12/489714
[patent_app_country] => US
[patent_app_date] => 2009-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
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[patent_no_of_words] => 19508
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[patent_words_short_claim] => 383
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/134/08134228.pdf
[firstpage_image] =>[orig_patent_app_number] => 12489714
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/489714 | Semiconductor device for battery power voltage control | Jun 22, 2009 | Issued |
Array
(
[id] => 8470412
[patent_doc_number] => 08299592
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-10-30
[patent_title] => 'Cube semiconductor package composed of a plurality of stacked together and interconnected semiconductor chip modules'
[patent_app_type] => utility
[patent_app_number] => 12/489626
[patent_app_country] => US
[patent_app_date] => 2009-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_claims] => 20
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12489626
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/489626 | Cube semiconductor package composed of a plurality of stacked together and interconnected semiconductor chip modules | Jun 22, 2009 | Issued |
Array
(
[id] => 8244828
[patent_doc_number] => 08202752
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-06-19
[patent_title] => 'Method for fabricating light emitting semiconductor device for reducing defects of dislocation in the device'
[patent_app_type] => utility
[patent_app_number] => 12/488875
[patent_app_country] => US
[patent_app_date] => 2009-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 5189
[patent_no_of_claims] => 9
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/202/08202752.pdf
[firstpage_image] =>[orig_patent_app_number] => 12488875
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/488875 | Method for fabricating light emitting semiconductor device for reducing defects of dislocation in the device | Jun 21, 2009 | Issued |
Array
(
[id] => 6247317
[patent_doc_number] => 20100025849
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-02-04
[patent_title] => 'COPPER ON ORGANIC SOLDERABILITY PRESERVATIVE (OSP) INTERCONNECT AND ENHANCED WIRE BONDING PROCESS'
[patent_app_type] => utility
[patent_app_number] => 12/489409
[patent_app_country] => US
[patent_app_date] => 2009-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 8062
[patent_no_of_claims] => 20
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[pdf_file] => publications/A1/0025/20100025849.pdf
[firstpage_image] =>[orig_patent_app_number] => 12489409
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/489409 | Copper on organic solderability preservative (OSP) interconnect and enhanced wire bonding process | Jun 21, 2009 | Issued |
Array
(
[id] => 8760677
[patent_doc_number] => 08421201
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-04-16
[patent_title] => 'Integrated circuit packaging system with underfill and methods of manufacture thereof'
[patent_app_type] => utility
[patent_app_number] => 12/489122
[patent_app_country] => US
[patent_app_date] => 2009-06-22
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 7370
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12489122
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/489122 | Integrated circuit packaging system with underfill and methods of manufacture thereof | Jun 21, 2009 | Issued |
Array
(
[id] => 6571341
[patent_doc_number] => 20100320590
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-23
[patent_title] => 'INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A LEADFRAME HAVING RADIAL-SEGMENTS AND METHOD OF MANUFACTURE THEREOF'
[patent_app_type] => utility
[patent_app_number] => 12/488043
[patent_app_country] => US
[patent_app_date] => 2009-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3558
[patent_no_of_claims] => 20
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[pdf_file] => publications/A1/0320/20100320590.pdf
[firstpage_image] =>[orig_patent_app_number] => 12488043
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/488043 | Integrated circuit packaging system with a leadframe having radial-segments and method of manufacture thereof | Jun 18, 2009 | Issued |
Array
(
[id] => 6478966
[patent_doc_number] => 20100213588
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-08-26
[patent_title] => 'WIRE BOND CHIP PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 12/485923
[patent_app_country] => US
[patent_app_date] => 2009-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3977
[patent_no_of_claims] => 22
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[pdf_file] => publications/A1/0213/20100213588.pdf
[firstpage_image] =>[orig_patent_app_number] => 12485923
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/485923 | WIRE BOND CHIP PACKAGE | Jun 16, 2009 | Abandoned |
Array
(
[id] => 4587170
[patent_doc_number] => 07851930
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-12-14
[patent_title] => 'Conductive adhesive compositions containing an alloy filler material for better dispense and thermal properties'
[patent_app_type] => utility
[patent_app_number] => 12/475634
[patent_app_country] => US
[patent_app_date] => 2009-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 9343
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[pdf_file] => patents/07/851/07851930.pdf
[firstpage_image] =>[orig_patent_app_number] => 12475634
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/475634 | Conductive adhesive compositions containing an alloy filler material for better dispense and thermal properties | May 31, 2009 | Issued |
Array
(
[id] => 8165869
[patent_doc_number] => 08174131
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-05-08
[patent_title] => 'Semiconductor device having a filled trench structure and methods for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 12/472884
[patent_app_country] => US
[patent_app_date] => 2009-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/08/174/08174131.pdf
[firstpage_image] =>[orig_patent_app_number] => 12472884
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/472884 | Semiconductor device having a filled trench structure and methods for fabricating the same | May 26, 2009 | Issued |
Array
(
[id] => 4533444
[patent_doc_number] => 07888184
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-15
[patent_title] => 'Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof'
[patent_app_type] => utility
[patent_app_number] => 12/473233
[patent_app_country] => US
[patent_app_date] => 2009-05-27
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[patent_drawing_sheets_cnt] => 11
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[pdf_file] => patents/07/888/07888184.pdf
[firstpage_image] =>[orig_patent_app_number] => 12473233
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/473233 | Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof | May 26, 2009 | Issued |
Array
(
[id] => 4604683
[patent_doc_number] => 07985663
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[patent_issue_date] => 2011-07-26
[patent_title] => 'Method for manufacturing a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 12/471923
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/471923 | Method for manufacturing a semiconductor device | May 25, 2009 | Issued |
Array
(
[id] => 8469756
[patent_doc_number] => 08298933
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[patent_title] => 'Conformal films on semiconductor substrates'
[patent_app_type] => utility
[patent_app_number] => 12/467200
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/467200 | Conformal films on semiconductor substrates | May 14, 2009 | Issued |
Array
(
[id] => 7527884
[patent_doc_number] => 08044479
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[patent_title] => 'Transistors, semiconductor devices, assemblies and constructions'
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[patent_app_number] => 12/424392
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[firstpage_image] =>[orig_patent_app_number] => 12424392
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/424392 | Transistors, semiconductor devices, assemblies and constructions | Apr 14, 2009 | Issued |
Array
(
[id] => 6264039
[patent_doc_number] => 20100252846
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-07
[patent_title] => 'BACKLIGHT INCLUDING SEMICONDUCTIOR LIGHT EMITTING DEVICES'
[patent_app_type] => utility
[patent_app_number] => 12/417673
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[firstpage_image] =>[orig_patent_app_number] => 12417673
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/417673 | Backlight including semiconductior light emitting devices | Apr 2, 2009 | Issued |
Array
(
[id] => 6575520
[patent_doc_number] => 20100096719
[patent_country] => US
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[patent_issue_date] => 2010-04-22
[patent_title] => 'METHODS OF FORMING FINE PATTERNS IN INTEGRATED CIRCUIT DEVICES'
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[patent_app_number] => 12/418023
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[pdf_file] => publications/A1/0096/20100096719.pdf
[firstpage_image] =>[orig_patent_app_number] => 12418023
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/418023 | Methods of forming fine patterns in integrated circuit devices | Apr 2, 2009 | Issued |
Array
(
[id] => 9245188
[patent_doc_number] => 08609467
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[patent_title] => 'Lead frame and method for manufacturing circuit device using the same'
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Array
(
[id] => 6320788
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/414884 | CMOS IMAGE SENSOR ON A SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND PROCESS FOR MAKING SAME | Mar 30, 2009 | Abandoned |
Array
(
[id] => 6501183
[patent_doc_number] => 20100012912
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[patent_issue_date] => 2010-01-21
[patent_title] => 'ELECTRONIC DEVICES INCLUDING CARBON-BASED FILMS HAVING SIDEWALL LINERS, AND METHODS OF FORMING SUCH DEVICES'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 12415964
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/415964 | Electronic devices including carbon-based films having sidewall liners, and methods of forming such devices | Mar 30, 2009 | Issued |
Array
(
[id] => 5578177
[patent_doc_number] => 20090173523
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[patent_issue_date] => 2009-07-09
[patent_title] => 'MULTILAYER BUILD-UP WIRING BOARD'
[patent_app_type] => utility
[patent_app_number] => 12/406009
[patent_app_country] => US
[patent_app_date] => 2009-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
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[pdf_file] => publications/A1/0173/20090173523.pdf
[firstpage_image] =>[orig_patent_app_number] => 12406009
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/406009 | Multilayer build-up wiring board including a chip mount region | Mar 16, 2009 | Issued |