Search

James R. Bidwell

Examiner (ID: 2020, Phone: (571)272-6910 , Office: P/3651 )

Most Active Art Unit
3651
Art Unit(s)
3651, 3615, 2899, 3107, 3101
Total Applications
4817
Issued Applications
4303
Pending Applications
229
Abandoned Applications
341

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12434028 [patent_doc_number] => 09977857 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-22 [patent_title] => Method and circuit for via pillar optimization [patent_app_type] => utility [patent_app_number] => 15/600410 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15600410 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/600410
Method and circuit for via pillar optimization May 18, 2017 Issued
Array ( [id] => 12195547 [patent_doc_number] => 09899283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Power module with low stray inductance' [patent_app_type] => utility [patent_app_number] => 15/599626 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5523 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599626 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/599626
Power module with low stray inductance May 18, 2017 Issued
Array ( [id] => 13571203 [patent_doc_number] => 20180337149 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/599480 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599480 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/599480
Semiconductor package and manufacturing method thereof May 18, 2017 Issued
Array ( [id] => 12597015 [patent_doc_number] => 20180090835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => ELECTRONIC PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/596113 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3910 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -50 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596113 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/596113
Electronic package structure and fabrication method thereof May 15, 2017 Issued
Array ( [id] => 12168398 [patent_doc_number] => 09887170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-06 [patent_title] => 'Multi-layer metal pads' [patent_app_type] => utility [patent_app_number] => 15/592941 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 6987 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592941 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/592941
Multi-layer metal pads May 10, 2017 Issued
Array ( [id] => 11939657 [patent_doc_number] => 20170243807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'PACKAGING FOR HIGH POWER INTEGRATED CIRCUITS AND INFRARED EMITTER ARRAYS' [patent_app_type] => utility [patent_app_number] => 15/589431 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4077 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589431 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589431
Packaging for high power integrated circuits and infrared emitter arrays May 7, 2017 Issued
Array ( [id] => 11939692 [patent_doc_number] => 20170243842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF' [patent_app_type] => utility [patent_app_number] => 15/589027 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4465 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589027 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589027
Semiconductor arrangement and formation thereof May 7, 2017 Issued
Array ( [id] => 13514531 [patent_doc_number] => 20180308808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => ACTIVE SHIELD FOR PROTECTING A DEVICE FROM BACKSIDE ATTACKS [patent_app_type] => utility [patent_app_number] => 15/496017 [patent_app_country] => US [patent_app_date] => 2017-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15496017 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/496017
Active shield for protecting a device from backside attacks Apr 24, 2017 Issued
Array ( [id] => 13514481 [patent_doc_number] => 20180308783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => DYNAMIC MOUNTING THERMAL MANAGEMENT FOR DEVICES ON BOARD [patent_app_type] => utility [patent_app_number] => 15/495720 [patent_app_country] => US [patent_app_date] => 2017-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8860 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15495720 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/495720
Dynamic mounting thermal management for devices on board Apr 23, 2017 Issued
Array ( [id] => 12477792 [patent_doc_number] => 09991185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Direct bonded copper semiconductor packages and related methods [patent_app_type] => utility [patent_app_number] => 15/489998 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 8628 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15489998 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/489998
Direct bonded copper semiconductor packages and related methods Apr 17, 2017 Issued
Array ( [id] => 11840090 [patent_doc_number] => 20170221810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'Self-Aligned Via and Plug Patterning for Back End of Line (BEOL) Interconnects' [patent_app_type] => utility [patent_app_number] => 15/490804 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10351 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15490804 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/490804
Self-aligned via and plug patterning for back end of line (BEOL) interconnects Apr 17, 2017 Issued
Array ( [id] => 11990196 [patent_doc_number] => 20170294351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'ELECTRICAL CONDUCTIVE VIAS IN A SEMICONDUCTOR SUBSTRATE AND A CORRESPONDING MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 15/483538 [patent_app_country] => US [patent_app_date] => 2017-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7278 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15483538 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/483538
Electrically conductive via(s) in a semiconductor substrate and associated production method Apr 9, 2017 Issued
Array ( [id] => 12236118 [patent_doc_number] => 20180068981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/483444 [patent_app_country] => US [patent_app_date] => 2017-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7483 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15483444 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/483444
Semiconductor apparatus and semiconductor system including the same Apr 9, 2017 Issued
Array ( [id] => 12181611 [patent_doc_number] => 20180040548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'SEMICONDUCTOR PACKAGE INCLUDING A REWIRING LAYER WITH AN EMBEDDED CHIP' [patent_app_type] => utility [patent_app_number] => 15/468294 [patent_app_country] => US [patent_app_date] => 2017-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9257 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15468294 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/468294
Semiconductor package including a rewiring layer with an embedded chip Mar 23, 2017 Issued
Array ( [id] => 13228779 [patent_doc_number] => 10128171 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-13 [patent_title] => Leadframe with improved half-etch layout to reduce defects caused during singulation [patent_app_type] => utility [patent_app_number] => 15/468827 [patent_app_country] => US [patent_app_date] => 2017-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3068 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15468827 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/468827
Leadframe with improved half-etch layout to reduce defects caused during singulation Mar 23, 2017 Issued
Array ( [id] => 13451843 [patent_doc_number] => 20180277464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => SEMICONDUCTOR DEVICE HAVING CORRUGATED LEADS AND METHOD FOR FORMING [patent_app_type] => utility [patent_app_number] => 15/468058 [patent_app_country] => US [patent_app_date] => 2017-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3389 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15468058 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/468058
Semiconductor device having corrugated leads and method for forming Mar 22, 2017 Issued
Array ( [id] => 13451703 [patent_doc_number] => 20180277394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => SEMICONDUCTOR DEVICE WITH TIERED PILLAR AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/467794 [patent_app_country] => US [patent_app_date] => 2017-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15467794 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/467794
Semiconductor device with tiered pillar and manufacturing method thereof Mar 22, 2017 Issued
Array ( [id] => 14151617 [patent_doc_number] => 10256198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Warpage control for microelectronics packages [patent_app_type] => utility [patent_app_number] => 15/468067 [patent_app_country] => US [patent_app_date] => 2017-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 8822 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15468067 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/468067
Warpage control for microelectronics packages Mar 22, 2017 Issued
Array ( [id] => 12436569 [patent_doc_number] => 09978707 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-22 [patent_title] => Electrical-device adhesive barrier [patent_app_type] => utility [patent_app_number] => 15/467659 [patent_app_country] => US [patent_app_date] => 2017-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2506 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15467659 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/467659
Electrical-device adhesive barrier Mar 22, 2017 Issued
Array ( [id] => 15921879 [patent_doc_number] => 10658187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Method for manufacturing a semiconductor component and a semiconductor component [patent_app_type] => utility [patent_app_number] => 16/081768 [patent_app_country] => US [patent_app_date] => 2017-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 5663 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16081768 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/081768
Method for manufacturing a semiconductor component and a semiconductor component Feb 28, 2017 Issued
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