Search

James R. Bidwell

Examiner (ID: 2020, Phone: (571)272-6910 , Office: P/3651 )

Most Active Art Unit
3651
Art Unit(s)
3651, 3615, 2899, 3107, 3101
Total Applications
4817
Issued Applications
4303
Pending Applications
229
Abandoned Applications
341

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10780046 [patent_doc_number] => 20160126202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'BRIDGING ARRANGEMENT, MICROELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING A BRIDGING ARRANGEMENT' [patent_app_type] => utility [patent_app_number] => 14/880648 [patent_app_country] => US [patent_app_date] => 2015-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4938 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14880648 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/880648
BRIDGING ARRANGEMENT, MICROELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING A BRIDGING ARRANGEMENT Oct 11, 2015 Abandoned
Array ( [id] => 11890925 [patent_doc_number] => 09761490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Method for forming contact holes in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/879066 [patent_app_country] => US [patent_app_date] => 2015-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14879066 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/879066
Method for forming contact holes in a semiconductor device Oct 7, 2015 Issued
Array ( [id] => 11007019 [patent_doc_number] => 20160203971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'GATE STACK MATERIALS FOR SEMICONDUCTOR APPLICATIONS FOR LITHOGRAPHIC OVERLAY IMPROVEMENT' [patent_app_type] => utility [patent_app_number] => 14/879043 [patent_app_country] => US [patent_app_date] => 2015-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14879043 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/879043
Gate stack materials for semiconductor applications for lithographic overlay improvement Oct 7, 2015 Issued
Array ( [id] => 11740193 [patent_doc_number] => 09704786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Direct selective adhesion promotor plating' [patent_app_type] => utility [patent_app_number] => 14/866050 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6074 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14866050 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/866050
Direct selective adhesion promotor plating Sep 24, 2015 Issued
Array ( [id] => 10495488 [patent_doc_number] => 20150380510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'STRUCTURE AND METHOD OF FORMING SILICIDE ON FINS' [patent_app_type] => utility [patent_app_number] => 14/849483 [patent_app_country] => US [patent_app_date] => 2015-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3530 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14849483 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/849483
STRUCTURE AND METHOD OF FORMING SILICIDE ON FINS Sep 8, 2015 Abandoned
Array ( [id] => 10479433 [patent_doc_number] => 20150364450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-17 [patent_title] => 'CO-SUPPORT FOR XFD PACKAGING' [patent_app_type] => utility [patent_app_number] => 14/837576 [patent_app_country] => US [patent_app_date] => 2015-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17046 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14837576 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/837576
Co-support for XFD packaging Aug 26, 2015 Issued
Array ( [id] => 11765161 [patent_doc_number] => 09373610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-21 [patent_title] => 'Process for forming package-on-package structures' [patent_app_type] => utility [patent_app_number] => 14/825722 [patent_app_country] => US [patent_app_date] => 2015-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 51 [patent_no_of_words] => 4462 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14825722 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/825722
Process for forming package-on-package structures Aug 12, 2015 Issued
Array ( [id] => 10455280 [patent_doc_number] => 20150340295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'Space and Cost Efficient Incorporation of Specialized Input-Output Pins on Integrated Circuit Substrates' [patent_app_type] => utility [patent_app_number] => 14/816611 [patent_app_country] => US [patent_app_date] => 2015-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3158 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14816611 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/816611
Space and cost efficient incorporation of specialized input-output pins on integrated circuit substrates Aug 2, 2015 Issued
Array ( [id] => 10753066 [patent_doc_number] => 20160099218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/815937 [patent_app_country] => US [patent_app_date] => 2015-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 11358 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14815937 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/815937
Semiconductor package and method of manufacturing the same Jul 30, 2015 Issued
Array ( [id] => 11883643 [patent_doc_number] => 09754825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-05 [patent_title] => 'Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods' [patent_app_type] => utility [patent_app_number] => 14/815560 [patent_app_country] => US [patent_app_date] => 2015-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 4035 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14815560 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/815560
Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods Jul 30, 2015 Issued
Array ( [id] => 10597345 [patent_doc_number] => 09318440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Formation of carbon-rich contact liner material' [patent_app_type] => utility [patent_app_number] => 14/799116 [patent_app_country] => US [patent_app_date] => 2015-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14799116 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/799116
Formation of carbon-rich contact liner material Jul 13, 2015 Issued
Array ( [id] => 11132320 [patent_doc_number] => 20160329295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'SEMICONDUCTOR-MOUNTED PRODUCT AND METHOD OF PRODUCING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/907256 [patent_app_country] => US [patent_app_date] => 2015-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 13543 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14907256 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/907256
Semiconductor-mounted product and method of producing the same Jul 8, 2015 Issued
Array ( [id] => 11194293 [patent_doc_number] => 09425111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'Semiconductor package' [patent_app_type] => utility [patent_app_number] => 14/751626 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14751626 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/751626
Semiconductor package Jun 25, 2015 Issued
Array ( [id] => 10402660 [patent_doc_number] => 20150287669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'METHOD OF MANUFACTURING RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE, AND LEAD FRAME' [patent_app_type] => utility [patent_app_number] => 14/741827 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3402 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14741827 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/741827
Method of manufacturing resin-encapsulated semiconductor device, and lead frame Jun 16, 2015 Issued
Array ( [id] => 13667169 [patent_doc_number] => 10163762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Lead frame with conductive clip for mounting a semiconductor die with reduced clip shifting [patent_app_type] => utility [patent_app_number] => 14/735229 [patent_app_country] => US [patent_app_date] => 2015-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2563 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14735229 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/735229
Lead frame with conductive clip for mounting a semiconductor die with reduced clip shifting Jun 9, 2015 Issued
Array ( [id] => 13772855 [patent_doc_number] => 10178786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Circuit packages including modules that include at least one integrated circuit [patent_app_type] => utility [patent_app_number] => 14/723813 [patent_app_country] => US [patent_app_date] => 2015-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14723813 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/723813
Circuit packages including modules that include at least one integrated circuit May 27, 2015 Issued
Array ( [id] => 13257047 [patent_doc_number] => 10141217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-27 [patent_title] => Dicing-tape integrated film for backside of semiconductor and method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 14/710696 [patent_app_country] => US [patent_app_date] => 2015-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 14919 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14710696 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/710696
Dicing-tape integrated film for backside of semiconductor and method of manufacturing semiconductor device May 12, 2015 Issued
Array ( [id] => 10638491 [patent_doc_number] => 09356002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-31 [patent_title] => 'Semiconductor package and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/706096 [patent_app_country] => US [patent_app_date] => 2015-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 8685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14706096 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/706096
Semiconductor package and method for manufacturing the same May 6, 2015 Issued
Array ( [id] => 10358636 [patent_doc_number] => 20150243641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/706052 [patent_app_country] => US [patent_app_date] => 2015-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2961 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14706052 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/706052
Integrated circuit package May 6, 2015 Issued
Array ( [id] => 10486911 [patent_doc_number] => 20150371932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-24 [patent_title] => 'THIN FILM RDL FOR NANOCHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/700624 [patent_app_country] => US [patent_app_date] => 2015-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 2910 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14700624 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/700624
Thin film RDL for nanochip package Apr 29, 2015 Issued
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