Search

James R. Bidwell

Examiner (ID: 2020, Phone: (571)272-6910 , Office: P/3651 )

Most Active Art Unit
3651
Art Unit(s)
3651, 3615, 2899, 3107, 3101
Total Applications
4817
Issued Applications
4303
Pending Applications
229
Abandoned Applications
341

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11043552 [patent_doc_number] => 20160240508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'Package Structures and Methods of Forming the Same' [patent_app_type] => utility [patent_app_number] => 14/696054 [patent_app_country] => US [patent_app_date] => 2015-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 9100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14696054 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/696054
Package structures and methods of forming the same Apr 23, 2015 Issued
Array ( [id] => 10343605 [patent_doc_number] => 20150228610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-13 [patent_title] => 'Semiconductor Package Including a Power Stage and Integrated Output Inductor' [patent_app_type] => utility [patent_app_number] => 14/694979 [patent_app_country] => US [patent_app_date] => 2015-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4566 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14694979 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/694979
Semiconductor package including a power stage and integrated output inductor Apr 22, 2015 Issued
Array ( [id] => 10652198 [patent_doc_number] => 09368463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/694199 [patent_app_country] => US [patent_app_date] => 2015-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 44 [patent_no_of_words] => 23992 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14694199 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/694199
Semiconductor device Apr 22, 2015 Issued
Array ( [id] => 10151821 [patent_doc_number] => 09184119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Lead frame with abutment surface' [patent_app_type] => utility [patent_app_number] => 14/691690 [patent_app_country] => US [patent_app_date] => 2015-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3210 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14691690 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/691690
Lead frame with abutment surface Apr 20, 2015 Issued
Array ( [id] => 10709907 [patent_doc_number] => 20160056055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE THEREOF' [patent_app_type] => utility [patent_app_number] => 14/692152 [patent_app_country] => US [patent_app_date] => 2015-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 15812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14692152 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/692152
Manufacturing method of semiconductor device and semiconductor device thereof Apr 20, 2015 Issued
Array ( [id] => 12102098 [patent_doc_number] => 09859197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Integrated circuit package fabrication' [patent_app_type] => utility [patent_app_number] => 14/691660 [patent_app_country] => US [patent_app_date] => 2015-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3211 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14691660 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/691660
Integrated circuit package fabrication Apr 20, 2015 Issued
Array ( [id] => 11233779 [patent_doc_number] => 09461014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Methods of forming ultra thin package structures including low temperature solder and structures formed therby' [patent_app_type] => utility [patent_app_number] => 14/686177 [patent_app_country] => US [patent_app_date] => 2015-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3520 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14686177 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/686177
Methods of forming ultra thin package structures including low temperature solder and structures formed therby Apr 13, 2015 Issued
Array ( [id] => 13060629 [patent_doc_number] => 10051733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Printed circuit board with coextensive electrical connectors and contact pad areas [patent_app_type] => utility [patent_app_number] => 14/684619 [patent_app_country] => US [patent_app_date] => 2015-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 4489 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14684619 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/684619
Printed circuit board with coextensive electrical connectors and contact pad areas Apr 12, 2015 Issued
Array ( [id] => 13228851 [patent_doc_number] => 10128207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Semiconductor packages with pillar and bump structures [patent_app_type] => utility [patent_app_number] => 14/674891 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3644 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14674891 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/674891
Semiconductor packages with pillar and bump structures Mar 30, 2015 Issued
Array ( [id] => 11087569 [patent_doc_number] => 20160284537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'SILICON-BASED MIDDLE LAYER COMPOSITION' [patent_app_type] => utility [patent_app_number] => 14/671696 [patent_app_country] => US [patent_app_date] => 2015-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4269 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14671696 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/671696
Silicon-based middle layer composition Mar 26, 2015 Issued
Array ( [id] => 10309404 [patent_doc_number] => 20150194406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-09 [patent_title] => 'HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE' [patent_app_type] => utility [patent_app_number] => 14/663689 [patent_app_country] => US [patent_app_date] => 2015-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14663689 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/663689
High density substrate routing in BBUL package Mar 19, 2015 Issued
Array ( [id] => 13754945 [patent_doc_number] => 10170426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Manufacturing method of wiring structure and wiring structure [patent_app_type] => utility [patent_app_number] => 14/661585 [patent_app_country] => US [patent_app_date] => 2015-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 29 [patent_no_of_words] => 6411 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14661585 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/661585
Manufacturing method of wiring structure and wiring structure Mar 17, 2015 Issued
Array ( [id] => 11079269 [patent_doc_number] => 20160276233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'System and Method for Dual-Region Singulation' [patent_app_type] => utility [patent_app_number] => 14/660753 [patent_app_country] => US [patent_app_date] => 2015-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5264 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14660753 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/660753
System and method for dual-region singulation Mar 16, 2015 Issued
Array ( [id] => 13201453 [patent_doc_number] => 10115647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Non-vertical through-via in package [patent_app_type] => utility [patent_app_number] => 14/658968 [patent_app_country] => US [patent_app_date] => 2015-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 5110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14658968 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/658968
Non-vertical through-via in package Mar 15, 2015 Issued
Array ( [id] => 11187486 [patent_doc_number] => 09418895 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-16 [patent_title] => 'Dies for RFID devices and sensor applications' [patent_app_type] => utility [patent_app_number] => 14/658151 [patent_app_country] => US [patent_app_date] => 2015-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 7534 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14658151 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/658151
Dies for RFID devices and sensor applications Mar 13, 2015 Issued
Array ( [id] => 10294624 [patent_doc_number] => 20150179624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'Process for Forming Package-on-Package Structures' [patent_app_type] => utility [patent_app_number] => 14/638839 [patent_app_country] => US [patent_app_date] => 2015-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 4437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14638839 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/638839
Process for forming package-on-package structures Mar 3, 2015 Issued
Array ( [id] => 10286045 [patent_doc_number] => 20150171043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'DIE-DIE STACKING STRUCTURE AND METHOD FOR MAKING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/633205 [patent_app_country] => US [patent_app_date] => 2015-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3746 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14633205 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/633205
Die-die stacking structure and method for making the same Feb 26, 2015 Issued
Array ( [id] => 10787437 [patent_doc_number] => 20160133593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/624642 [patent_app_country] => US [patent_app_date] => 2015-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2902 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14624642 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/624642
Electronic package and fabrication method thereof Feb 17, 2015 Issued
Array ( [id] => 10350997 [patent_doc_number] => 20150236002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-20 [patent_title] => 'MULTI-CHIP MODULE WITH STACKED FACE-DOWN CONNECTED DIES' [patent_app_type] => utility [patent_app_number] => 14/623161 [patent_app_country] => US [patent_app_date] => 2015-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10974 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14623161 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/623161
Multi-chip module with stacked face-down connected dies Feb 15, 2015 Issued
Array ( [id] => 10617721 [patent_doc_number] => 09337170 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-10 [patent_title] => 'Contact arrangements for stackable microelectronic package structures' [patent_app_type] => utility [patent_app_number] => 14/609878 [patent_app_country] => US [patent_app_date] => 2015-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 12500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609878 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/609878
Contact arrangements for stackable microelectronic package structures Jan 29, 2015 Issued
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