
James R. Bidwell
Examiner (ID: 2020, Phone: (571)272-6910 , Office: P/3651 )
| Most Active Art Unit | 3651 |
| Art Unit(s) | 3651, 3615, 2899, 3107, 3101 |
| Total Applications | 4817 |
| Issued Applications | 4303 |
| Pending Applications | 229 |
| Abandoned Applications | 341 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11637853
[patent_doc_number] => 09659837
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-23
[patent_title] => 'Direct bonded copper semiconductor packages and related methods'
[patent_app_type] => utility
[patent_app_number] => 14/610115
[patent_app_country] => US
[patent_app_date] => 2015-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 16
[patent_no_of_words] => 8752
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14610115
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/610115 | Direct bonded copper semiconductor packages and related methods | Jan 29, 2015 | Issued |
Array
(
[id] => 10631550
[patent_doc_number] => 09349707
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-05-24
[patent_title] => 'Contact arrangements for stackable microelectronic package structures with multiple ranks'
[patent_app_type] => utility
[patent_app_number] => 14/609896
[patent_app_country] => US
[patent_app_date] => 2015-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 29
[patent_no_of_words] => 12439
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14609896
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/609896 | Contact arrangements for stackable microelectronic package structures with multiple ranks | Jan 29, 2015 | Issued |
Array
(
[id] => 11578677
[patent_doc_number] => 09633947
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-04-25
[patent_title] => 'Folded ballistic conductor interconnect line'
[patent_app_type] => utility
[patent_app_number] => 14/608337
[patent_app_country] => US
[patent_app_date] => 2015-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2591
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 36
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14608337
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/608337 | Folded ballistic conductor interconnect line | Jan 28, 2015 | Issued |
Array
(
[id] => 11898194
[patent_doc_number] => 09768134
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-09-19
[patent_title] => 'Methods of forming conductive materials on semiconductor devices, and methods of forming electrical interconnects'
[patent_app_type] => utility
[patent_app_number] => 14/608466
[patent_app_country] => US
[patent_app_date] => 2015-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 6413
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14608466
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/608466 | Methods of forming conductive materials on semiconductor devices, and methods of forming electrical interconnects | Jan 28, 2015 | Issued |
Array
(
[id] => 10442398
[patent_doc_number] => 20150327410
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-11-12
[patent_title] => 'DEVICE PACKAGE AND METHODS FOR THE FABRICATION THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/601629
[patent_app_country] => US
[patent_app_date] => 2015-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7557
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14601629
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/601629 | DEVICE PACKAGE AND METHODS FOR THE FABRICATION THEREOF | Jan 20, 2015 | |
Array
(
[id] => 13201465
[patent_doc_number] => 10115653
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-30
[patent_title] => Thermal dissipation through seal rings in 3DIC structure
[patent_app_type] => utility
[patent_app_number] => 14/599834
[patent_app_country] => US
[patent_app_date] => 2015-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 4671
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14599834
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/599834 | Thermal dissipation through seal rings in 3DIC structure | Jan 18, 2015 | Issued |
Array
(
[id] => 10315187
[patent_doc_number] => 20150200190
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-16
[patent_title] => 'Package on Packaging Structure and Methods of Making Same'
[patent_app_type] => utility
[patent_app_number] => 14/592587
[patent_app_country] => US
[patent_app_date] => 2015-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2998
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14592587
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/592587 | Package on packaging structure and methods of making same | Jan 7, 2015 | Issued |
Array
(
[id] => 10309330
[patent_doc_number] => 20150194331
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-09
[patent_title] => 'CYCLIC OLEFIN POLYMER COMPOSITIONS AND POLYSILOXANE RELEASE LAYERS FOR USE IN TEMPORARY WAFER BONDING PROCESSES'
[patent_app_type] => utility
[patent_app_number] => 14/590531
[patent_app_country] => US
[patent_app_date] => 2015-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8300
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14590531
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/590531 | Cyclic olefin polymer compositions and polysiloxane release layers for use in temporary wafer bonding processes | Jan 5, 2015 | Issued |
Array
(
[id] => 10617638
[patent_doc_number] => 09337087
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-05-10
[patent_title] => 'Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the same'
[patent_app_type] => utility
[patent_app_number] => 14/586688
[patent_app_country] => US
[patent_app_date] => 2014-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 25
[patent_no_of_words] => 6175
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14586688
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/586688 | Multilayer structure in an integrated circuit for damage prevention and detection and methods of creating the same | Dec 29, 2014 | Issued |
Array
(
[id] => 10525562
[patent_doc_number] => 09252082
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-02
[patent_title] => 'Semiconductor device, circuit substrate, and electronic device'
[patent_app_type] => utility
[patent_app_number] => 14/584591
[patent_app_country] => US
[patent_app_date] => 2014-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 5903
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14584591
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/584591 | Semiconductor device, circuit substrate, and electronic device | Dec 28, 2014 | Issued |
Array
(
[id] => 11817960
[patent_doc_number] => 09721918
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-01
[patent_title] => 'Contact area design for solder bonding'
[patent_app_type] => utility
[patent_app_number] => 14/584748
[patent_app_country] => US
[patent_app_date] => 2014-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 46
[patent_no_of_words] => 7383
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14584748
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/584748 | Contact area design for solder bonding | Dec 28, 2014 | Issued |
Array
(
[id] => 11817960
[patent_doc_number] => 09721918
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-01
[patent_title] => 'Contact area design for solder bonding'
[patent_app_type] => utility
[patent_app_number] => 14/584748
[patent_app_country] => US
[patent_app_date] => 2014-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 46
[patent_no_of_words] => 7383
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14584748
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/584748 | Contact area design for solder bonding | Dec 28, 2014 | Issued |
Array
(
[id] => 11817960
[patent_doc_number] => 09721918
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-01
[patent_title] => 'Contact area design for solder bonding'
[patent_app_type] => utility
[patent_app_number] => 14/584748
[patent_app_country] => US
[patent_app_date] => 2014-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 46
[patent_no_of_words] => 7383
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14584748
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/584748 | Contact area design for solder bonding | Dec 28, 2014 | Issued |
Array
(
[id] => 11817960
[patent_doc_number] => 09721918
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-08-01
[patent_title] => 'Contact area design for solder bonding'
[patent_app_type] => utility
[patent_app_number] => 14/584748
[patent_app_country] => US
[patent_app_date] => 2014-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 46
[patent_no_of_words] => 7383
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14584748
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/584748 | Contact area design for solder bonding | Dec 28, 2014 | Issued |
Array
(
[id] => 10531234
[patent_doc_number] => 09257374
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-02-09
[patent_title] => 'Thin shrink outline package (TSOP)'
[patent_app_type] => utility
[patent_app_number] => 14/582521
[patent_app_country] => US
[patent_app_date] => 2014-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 2593
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14582521
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/582521 | Thin shrink outline package (TSOP) | Dec 23, 2014 | Issued |
Array
(
[id] => 13005957
[patent_doc_number] => 10026649
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-17
[patent_title] => Decoupled via fill
[patent_app_type] => utility
[patent_app_number] => 15/528425
[patent_app_country] => US
[patent_app_date] => 2014-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 6362
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15528425
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/528425 | Decoupled via fill | Dec 22, 2014 | Issued |
Array
(
[id] => 12054450
[patent_doc_number] => 20170330794
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-16
[patent_title] => 'VIA BLOCKING LAYER'
[patent_app_type] => utility
[patent_app_number] => 15/528427
[patent_app_country] => US
[patent_app_date] => 2014-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8533
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15528427
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/528427 | Via blocking layer | Dec 22, 2014 | Issued |
Array
(
[id] => 10984224
[patent_doc_number] => 20160181169
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-23
[patent_title] => 'ORGANIC-INORGANIC HYBRID STRUCTURE FOR INTEGRATED CIRCUIT PACKAGES'
[patent_app_type] => utility
[patent_app_number] => 14/581575
[patent_app_country] => US
[patent_app_date] => 2014-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5732
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14581575
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/581575 | Organic-inorganic hybrid structure for integrated circuit packages | Dec 22, 2014 | Issued |
Array
(
[id] => 10984268
[patent_doc_number] => 20160181213
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-23
[patent_title] => 'WAFER STRUCTURE AND METHOD FOR WAFER DICING'
[patent_app_type] => utility
[patent_app_number] => 14/577141
[patent_app_country] => US
[patent_app_date] => 2014-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 3312
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14577141
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/577141 | Wafer structure and method for wafer dicing | Dec 18, 2014 | Issued |
Array
(
[id] => 10766981
[patent_doc_number] => 20160113138
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-04-21
[patent_title] => 'LOW COST HIGH STRENGTH SURFACE MOUNT PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 14/573631
[patent_app_country] => US
[patent_app_date] => 2014-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3162
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14573631
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/573631 | Low cost high strength surface mount package | Dec 16, 2014 | Issued |