Search

Jami Valentine Miller

Examiner (ID: 17527, Phone: (571)272-9786 , Office: P/2894 )

Most Active Art Unit
2894
Art Unit(s)
2894, 2815, 2818
Total Applications
1537
Issued Applications
1403
Pending Applications
89
Abandoned Applications
70

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12147665 [patent_doc_number] => 09881924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-30 [patent_title] => 'Semiconductor memory device having coplanar digit line contacts and storage node contacts in memory array and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 15/151503 [patent_app_country] => US [patent_app_date] => 2016-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 7866 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15151503 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/151503
Semiconductor memory device having coplanar digit line contacts and storage node contacts in memory array and method for fabricating the same May 10, 2016 Issued
Array ( [id] => 13085273 [patent_doc_number] => 10062710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Integrated circuits with deep and ultra shallow trench isolations and methods for fabricating the same [patent_app_type] => utility [patent_app_number] => 15/151564 [patent_app_country] => US [patent_app_date] => 2016-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15151564 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/151564
Integrated circuits with deep and ultra shallow trench isolations and methods for fabricating the same May 10, 2016 Issued
Array ( [id] => 12012846 [patent_doc_number] => 09806170 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-31 [patent_title] => 'Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI' [patent_app_type] => utility [patent_app_number] => 15/151550 [patent_app_country] => US [patent_app_date] => 2016-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 31 [patent_no_of_words] => 5748 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15151550 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/151550
Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI May 10, 2016 Issued
Array ( [id] => 15015293 [patent_doc_number] => 10453805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Protection structure for semiconductor device package [patent_app_type] => utility [patent_app_number] => 15/147401 [patent_app_country] => US [patent_app_date] => 2016-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 57 [patent_no_of_words] => 5447 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15147401 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/147401
Protection structure for semiconductor device package May 4, 2016 Issued
Array ( [id] => 12355785 [patent_doc_number] => 09954109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Vertical transistor including controlled gate length and a self-aligned junction [patent_app_type] => utility [patent_app_number] => 15/147342 [patent_app_country] => US [patent_app_date] => 2016-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6088 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15147342 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/147342
Vertical transistor including controlled gate length and a self-aligned junction May 4, 2016 Issued
Array ( [id] => 12033845 [patent_doc_number] => 20170323944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'SPLIT FIN FIELD EFFECT TRANSISTOR ENABLING BACK BIAS ON FIN TYPE FIELD EFFECT TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 15/147245 [patent_app_country] => US [patent_app_date] => 2016-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8932 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15147245 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/147245
Split fin field effect transistor enabling back bias on fin type field effect transistors May 4, 2016 Issued
Array ( [id] => 12019855 [patent_doc_number] => 09812567 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-07 [patent_title] => 'Precise control of vertical transistor gate length' [patent_app_type] => utility [patent_app_number] => 15/147194 [patent_app_country] => US [patent_app_date] => 2016-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5339 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15147194 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/147194
Precise control of vertical transistor gate length May 4, 2016 Issued
Array ( [id] => 11270317 [patent_doc_number] => 20160332864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'MULTI-LEVEL MICROMECHANICAL STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/147197 [patent_app_country] => US [patent_app_date] => 2016-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17089 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15147197 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/147197
Multi-level micromechanical structure May 4, 2016 Issued
Array ( [id] => 11111115 [patent_doc_number] => 20160308085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'STACKED OPTOCOUPLER COMPONENT' [patent_app_type] => utility [patent_app_number] => 15/131121 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3349 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15131121 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/131121
Stacked optocoupler component Apr 17, 2016 Issued
Array ( [id] => 11563042 [patent_doc_number] => 09625626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Display motherboard and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 15/130247 [patent_app_country] => US [patent_app_date] => 2016-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4353 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15130247 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/130247
Display motherboard and manufacturing method thereof Apr 14, 2016 Issued
Array ( [id] => 13006083 [patent_doc_number] => 10026716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => 3DIC formation with dies bonded to formed RDLs [patent_app_type] => utility [patent_app_number] => 15/130460 [patent_app_country] => US [patent_app_date] => 2016-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 5437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15130460 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/130460
3DIC formation with dies bonded to formed RDLs Apr 14, 2016 Issued
Array ( [id] => 11811646 [patent_doc_number] => 09716222 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-25 [patent_title] => 'Semiconductor structure and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 15/130159 [patent_app_country] => US [patent_app_date] => 2016-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5387 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15130159 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/130159
Semiconductor structure and method for manufacturing the same Apr 14, 2016 Issued
Array ( [id] => 11411680 [patent_doc_number] => 09558992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Metal wiring of semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 15/090914 [patent_app_country] => US [patent_app_date] => 2016-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 8463 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15090914 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/090914
Metal wiring of semiconductor device and method for manufacturing the same Apr 4, 2016 Issued
Array ( [id] => 11417514 [patent_doc_number] => 09564346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-07 [patent_title] => 'Package carrier, semiconductor package, and process for fabricating same' [patent_app_type] => utility [patent_app_number] => 15/088683 [patent_app_country] => US [patent_app_date] => 2016-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 5938 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15088683 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/088683
Package carrier, semiconductor package, and process for fabricating same Mar 31, 2016 Issued
Array ( [id] => 11339667 [patent_doc_number] => 20160365423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 15/068573 [patent_app_country] => US [patent_app_date] => 2016-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3180 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15068573 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/068573
Semiconductor device and manufacturing method therefor Mar 11, 2016 Issued
Array ( [id] => 11840170 [patent_doc_number] => 20170221890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'METHOD AND DEVICE OF PREVENTING MERGING OF RESIST-PROTECTION-OXIDE (RPO) BETWEEN ADJACENT STRUCTURES' [patent_app_type] => utility [patent_app_number] => 15/064647 [patent_app_country] => US [patent_app_date] => 2016-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6089 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15064647 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/064647
Method and device of preventing merging of resist-protection-oxide (RPO) between adjacent structures Mar 8, 2016 Issued
Array ( [id] => 14769737 [patent_doc_number] => 10396274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Spin electronics element and method of manufacturing thereof [patent_app_type] => utility [patent_app_number] => 15/064586 [patent_app_country] => US [patent_app_date] => 2016-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 50 [patent_no_of_words] => 9949 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15064586 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/064586
Spin electronics element and method of manufacturing thereof Mar 7, 2016 Issued
Array ( [id] => 13257391 [patent_doc_number] => 10141393 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-27 [patent_title] => Three dimensional capacitor [patent_app_type] => utility [patent_app_number] => 15/060249 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3995 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15060249 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/060249
Three dimensional capacitor Mar 2, 2016 Issued
Array ( [id] => 12102030 [patent_doc_number] => 09859129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Semiconductor device and manufacturing method of the same' [patent_app_type] => utility [patent_app_number] => 15/054142 [patent_app_country] => US [patent_app_date] => 2016-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6883 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15054142 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/054142
Semiconductor device and manufacturing method of the same Feb 25, 2016 Issued
Array ( [id] => 11898134 [patent_doc_number] => 09768073 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-19 [patent_title] => 'Semiconductor device having dual channels, complementary semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 15/054134 [patent_app_country] => US [patent_app_date] => 2016-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 7219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15054134 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/054134
Semiconductor device having dual channels, complementary semiconductor device and manufacturing method thereof Feb 25, 2016 Issued
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