Search

Jan H. Silbaugh

Examiner (ID: 11269)

Most Active Art Unit
1307
Art Unit(s)
1307, 1407, 1732
Total Applications
573
Issued Applications
450
Pending Applications
5
Abandoned Applications
118

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8923900 [patent_doc_number] => 08489849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-16 [patent_title] => 'Method for paramaterized application specific integrated circuit (ASIC)/field programmable gate array (FPGA) memory-based ternary content addressable memory (TCAM)' [patent_app_type] => utility [patent_app_number] => 12/953952 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3148 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12953952 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/953952
Method for paramaterized application specific integrated circuit (ASIC)/field programmable gate array (FPGA) memory-based ternary content addressable memory (TCAM) Nov 23, 2010 Issued
Array ( [id] => 6147303 [patent_doc_number] => 20110131375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'Command Tag Checking in a Multi-Initiator Media Controller Architecture' [patent_app_type] => utility [patent_app_number] => 12/952207 [patent_app_country] => US [patent_app_date] => 2010-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 25909 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20110131375.pdf [firstpage_image] =>[orig_patent_app_number] => 12952207 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/952207
Command tag checking in a multi-initiator media controller architecture Nov 22, 2010 Issued
Array ( [id] => 8213834 [patent_doc_number] => 20120131282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'Providing A Directory Cache For Peripheral Devices' [patent_app_type] => utility [patent_app_number] => 12/953120 [patent_app_country] => US [patent_app_date] => 2010-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4639 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20120131282.pdf [firstpage_image] =>[orig_patent_app_number] => 12953120 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/953120
Providing a directory cache for peripheral devices Nov 22, 2010 Issued
Array ( [id] => 8985064 [patent_doc_number] => 08516194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Systems and methods for caching data with a nonvolatile memory cache' [patent_app_type] => utility [patent_app_number] => 12/951604 [patent_app_country] => US [patent_app_date] => 2010-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5769 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12951604 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/951604
Systems and methods for caching data with a nonvolatile memory cache Nov 21, 2010 Issued
Array ( [id] => 8623232 [patent_doc_number] => 08356153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-15 [patent_title] => 'Adaptive wear leveling via monitoring the properties of memory reference stream' [patent_app_type] => utility [patent_app_number] => 12/950522 [patent_app_country] => US [patent_app_date] => 2010-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7354 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12950522 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/950522
Adaptive wear leveling via monitoring the properties of memory reference stream Nov 18, 2010 Issued
Array ( [id] => 9444131 [patent_doc_number] => 08713263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Out-of-order load/store queue structure' [patent_app_type] => utility [patent_app_number] => 12/916672 [patent_app_country] => US [patent_app_date] => 2010-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8864 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12916672 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/916672
Out-of-order load/store queue structure Oct 31, 2010 Issued
Array ( [id] => 8752037 [patent_doc_number] => 08417880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'System for NAND flash parameter auto-detection' [patent_app_type] => utility [patent_app_number] => 12/916652 [patent_app_country] => US [patent_app_date] => 2010-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5801 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12916652 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/916652
System for NAND flash parameter auto-detection Oct 31, 2010 Issued
Array ( [id] => 8162579 [patent_doc_number] => 20120102289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'ORGANIZATION OF A SMALL OBJECT AREA AND A LARGE OBJECT AREA IN A JAVA HEAP' [patent_app_type] => utility [patent_app_number] => 12/909217 [patent_app_country] => US [patent_app_date] => 2010-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7113 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20120102289.pdf [firstpage_image] =>[orig_patent_app_number] => 12909217 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/909217
Organization of a small object area and a large object area in a java heap Oct 20, 2010 Issued
Array ( [id] => 8958980 [patent_doc_number] => 08504774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Dynamic cache configuration using separate read and write caches' [patent_app_type] => utility [patent_app_number] => 12/903834 [patent_app_country] => US [patent_app_date] => 2010-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6909 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12903834 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/903834
Dynamic cache configuration using separate read and write caches Oct 12, 2010 Issued
Array ( [id] => 8109295 [patent_doc_number] => 08156302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-10 [patent_title] => 'Integrating data from symmetric and asymmetric memory' [patent_app_type] => utility [patent_app_number] => 12/899709 [patent_app_country] => US [patent_app_date] => 2010-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/156/08156302.pdf [firstpage_image] =>[orig_patent_app_number] => 12899709 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/899709
Integrating data from symmetric and asymmetric memory Oct 6, 2010 Issued
Array ( [id] => 8109269 [patent_doc_number] => 08156288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-10 [patent_title] => 'Asymmetric memory migration in hybrid main memory' [patent_app_type] => utility [patent_app_number] => 12/853135 [patent_app_country] => US [patent_app_date] => 2010-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/156/08156288.pdf [firstpage_image] =>[orig_patent_app_number] => 12853135 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/853135
Asymmetric memory migration in hybrid main memory Aug 8, 2010 Issued
Array ( [id] => 6100392 [patent_doc_number] => 20110004730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'CACHE MEMORY DEVICE, PROCESSOR, AND CONTROL METHOD FOR CACHE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/826967 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 13021 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20110004730.pdf [firstpage_image] =>[orig_patent_app_number] => 12826967 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/826967
Cache memory device, processor, and control method for cache memory device to reduce power unnecessarily consumed by cache memory Jun 29, 2010 Issued
Array ( [id] => 7714081 [patent_doc_number] => 20120005403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'RECOVERY SCHEME FOR AN EMULATED MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/826814 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7798 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20120005403.pdf [firstpage_image] =>[orig_patent_app_number] => 12826814 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/826814
Recovery scheme for an emulated memory system Jun 29, 2010 Issued
Array ( [id] => 8460838 [patent_doc_number] => 08296521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Method of configuring non-volatile memory for a hybrid disk drive' [patent_app_type] => utility [patent_app_number] => 12/827718 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 13566 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12827718 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/827718
Method of configuring non-volatile memory for a hybrid disk drive Jun 29, 2010 Issued
Array ( [id] => 7714148 [patent_doc_number] => 20120005448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'Demand-Based Memory Management of Non-pagable Data Storage' [patent_app_type] => utility [patent_app_number] => 12/827063 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3646 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20120005448.pdf [firstpage_image] =>[orig_patent_app_number] => 12827063 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/827063
Demand-based memory management of non-pagable data storage Jun 29, 2010 Issued
Array ( [id] => 8878694 [patent_doc_number] => 08473678 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-25 [patent_title] => 'Managing multi-tiered storage pool provisioning' [patent_app_type] => utility [patent_app_number] => 12/826434 [patent_app_country] => US [patent_app_date] => 2010-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12826434 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/826434
Managing multi-tiered storage pool provisioning Jun 28, 2010 Issued
Array ( [id] => 6553878 [patent_doc_number] => 20100205362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'Cache Control in a Non-Volatile Memory Device' [patent_app_type] => utility [patent_app_number] => 12/767094 [patent_app_country] => US [patent_app_date] => 2010-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5105 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20100205362.pdf [firstpage_image] =>[orig_patent_app_number] => 12767094 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/767094
Flash memory and method for a cache portion storing less bit per cell than a main portion Apr 25, 2010 Issued
Array ( [id] => 8010811 [patent_doc_number] => 08086823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Method for speeding up page table address update on virtual machine' [patent_app_type] => utility [patent_app_number] => 12/766430 [patent_app_country] => US [patent_app_date] => 2010-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 41 [patent_no_of_words] => 17542 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086823.pdf [firstpage_image] =>[orig_patent_app_number] => 12766430 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/766430
Method for speeding up page table address update on virtual machine Apr 22, 2010 Issued
Array ( [id] => 4539751 [patent_doc_number] => 07953941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Data processor with memory controller having burst access operation' [patent_app_type] => utility [patent_app_number] => 12/728200 [patent_app_country] => US [patent_app_date] => 2010-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7286 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 486 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/953/07953941.pdf [firstpage_image] =>[orig_patent_app_number] => 12728200 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/728200
Data processor with memory controller having burst access operation Mar 19, 2010 Issued
Array ( [id] => 4510665 [patent_doc_number] => 07949828 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Data storage control on storage devices' [patent_app_type] => utility [patent_app_number] => 12/704463 [patent_app_country] => US [patent_app_date] => 2010-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 35 [patent_no_of_words] => 10673 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/949/07949828.pdf [firstpage_image] =>[orig_patent_app_number] => 12704463 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/704463
Data storage control on storage devices Feb 10, 2010 Issued
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