Search

Jane J. Zara

Examiner (ID: 10304, Phone: (571)272-0765 , Office: P/1674 )

Most Active Art Unit
1635
Art Unit(s)
1674, 1637, 1635
Total Applications
1878
Issued Applications
1057
Pending Applications
273
Abandoned Applications
588

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8087593 [patent_doc_number] => 08151130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-03 [patent_title] => 'Plural voltage level detection upon power drop for switching to standby mode with or without complete state saving interrupt processing' [patent_app_type] => utility [patent_app_number] => 12/379732 [patent_app_country] => US [patent_app_date] => 2009-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10293 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/151/08151130.pdf [firstpage_image] =>[orig_patent_app_number] => 12379732 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/379732
Plural voltage level detection upon power drop for switching to standby mode with or without complete state saving interrupt processing Feb 26, 2009 Issued
Array ( [id] => 6523426 [patent_doc_number] => 20100211757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'Systolic Data Processing Apparatus and Method' [patent_app_type] => utility [patent_app_number] => 12/372469 [patent_app_country] => US [patent_app_date] => 2009-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3663 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20100211757.pdf [firstpage_image] =>[orig_patent_app_number] => 12372469 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/372469
Sequentially propagating instructions of thread through serially coupled PEs for concurrent processing respective thread on different data and synchronizing upon branch Feb 16, 2009 Issued
Array ( [id] => 8716103 [patent_doc_number] => 08402254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Flag generation and use in processor with same processing for operation on small size operand as low order bits portion of operation on large size operand' [patent_app_type] => utility [patent_app_number] => 12/369075 [patent_app_country] => US [patent_app_date] => 2009-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 9959 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12369075 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/369075
Flag generation and use in processor with same processing for operation on small size operand as low order bits portion of operation on large size operand Feb 10, 2009 Issued
Array ( [id] => 9781279 [patent_doc_number] => 08856500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Obfuscating program by scattering sequential instructions into memory regions such that jumps occur with steps of both signs in equal frequency' [patent_app_type] => utility [patent_app_number] => 12/866394 [patent_app_country] => US [patent_app_date] => 2009-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 10529 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12866394 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/866394
Obfuscating program by scattering sequential instructions into memory regions such that jumps occur with steps of both signs in equal frequency Feb 1, 2009 Issued
Array ( [id] => 5565826 [patent_doc_number] => 20090138679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'Enhanced Boolean Processor' [patent_app_type] => utility [patent_app_number] => 12/364047 [patent_app_country] => US [patent_app_date] => 2009-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 55 [patent_no_of_words] => 43965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20090138679.pdf [firstpage_image] =>[orig_patent_app_number] => 12364047 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/364047
Short-circuit evaluation of Boolean expression by rolling up sub-expression result in registers storing default value Feb 1, 2009 Issued
Array ( [id] => 6479422 [patent_doc_number] => 20100191993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'LOGICAL POWER THROTTLING' [patent_app_type] => utility [patent_app_number] => 12/361422 [patent_app_country] => US [patent_app_date] => 2009-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6587 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20100191993.pdf [firstpage_image] =>[orig_patent_app_number] => 12361422 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/361422
Reducing temperature and power by instruction throttling at decode stage of processor pipeline in time constant duration steps Jan 27, 2009 Issued
Array ( [id] => 6478951 [patent_doc_number] => 20100191943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'COORDINATION BETWEEN A BRANCH-TARGET-BUFFER CIRCUIT AND AN INSTRUCTION CACHE' [patent_app_type] => utility [patent_app_number] => 12/359761 [patent_app_country] => US [patent_app_date] => 2009-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20100191943.pdf [firstpage_image] =>[orig_patent_app_number] => 12359761 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/359761
COORDINATION BETWEEN A BRANCH-TARGET-BUFFER CIRCUIT AND AN INSTRUCTION CACHE Jan 25, 2009 Abandoned
Array ( [id] => 4646937 [patent_doc_number] => 08024550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-20 [patent_title] => 'SIMD processor with each processing element receiving buffered control signal from clocked register positioned in the middle of the group' [patent_app_type] => utility [patent_app_number] => 12/356676 [patent_app_country] => US [patent_app_date] => 2009-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5314 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/024/08024550.pdf [firstpage_image] =>[orig_patent_app_number] => 12356676 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/356676
SIMD processor with each processing element receiving buffered control signal from clocked register positioned in the middle of the group Jan 20, 2009 Issued
Array ( [id] => 6234347 [patent_doc_number] => 20100185882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'Computer System Power Management Based on Task Criticality' [patent_app_type] => utility [patent_app_number] => 12/354816 [patent_app_country] => US [patent_app_date] => 2009-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6739 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20100185882.pdf [firstpage_image] =>[orig_patent_app_number] => 12354816 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/354816
Reducing power consumption of components based on criticality of running tasks independent of scheduling priority in multitask computer Jan 15, 2009 Issued
Array ( [id] => 5356405 [patent_doc_number] => 20090187749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'PIPELINE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/352154 [patent_app_country] => US [patent_app_date] => 2009-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20090187749.pdf [firstpage_image] =>[orig_patent_app_number] => 12352154 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/352154
Pipeline processor with write control and validity flags for controlling write-back of execution result data stored in pipeline buffer register Jan 11, 2009 Issued
Array ( [id] => 7734555 [patent_doc_number] => 08103856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration' [patent_app_type] => utility [patent_app_number] => 12/352493 [patent_app_country] => US [patent_app_date] => 2009-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8822 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/103/08103856.pdf [firstpage_image] =>[orig_patent_app_number] => 12352493 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/352493
Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration Jan 11, 2009 Issued
Array ( [id] => 4572703 [patent_doc_number] => 07962729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Dynamic runtime range checking of different types on a register using upper and lower bound value registers for the register' [patent_app_type] => utility [patent_app_number] => 12/348712 [patent_app_country] => US [patent_app_date] => 2009-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7099 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/962/07962729.pdf [firstpage_image] =>[orig_patent_app_number] => 12348712 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/348712
Dynamic runtime range checking of different types on a register using upper and lower bound value registers for the register Jan 4, 2009 Issued
Array ( [id] => 5332703 [patent_doc_number] => 20090113180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Fetch Director Employing Barrel-Incrementer-Based Round-Robin Apparatus For Use In Multithreading Microprocessor' [patent_app_type] => utility [patent_app_number] => 12/346652 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 28731 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20090113180.pdf [firstpage_image] =>[orig_patent_app_number] => 12346652 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/346652
Thread instruction fetch based on prioritized selection from plural round-robin outputs for different thread states Dec 29, 2008 Issued
Array ( [id] => 5317617 [patent_doc_number] => 20090282215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'MULTI-PROCESSOR SYSTEM AND MULTI-PROCESSING METHOD IN MULTI-PROCESSOR SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/346803 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3379 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282215.pdf [firstpage_image] =>[orig_patent_app_number] => 12346803 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/346803
MULTI-PROCESSOR SYSTEM AND MULTI-PROCESSING METHOD IN MULTI-PROCESSOR SYSTEM Dec 29, 2008 Abandoned
Array ( [id] => 6301964 [patent_doc_number] => 20100161949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'SYSTEM AND METHOD FOR FAST BRANCHING USING A PROGRAMMABLE BRANCH TABLE' [patent_app_type] => utility [patent_app_number] => 12/342851 [patent_app_country] => US [patent_app_date] => 2008-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20100161949.pdf [firstpage_image] =>[orig_patent_app_number] => 12342851 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/342851
Fast execution of branch instruction with multiple conditional expressions using programmable branch offset table Dec 22, 2008 Issued
Array ( [id] => 6301937 [patent_doc_number] => 20100161938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'System-On-A-Chip Supporting A Networked Array Of Configurable Symmetric Multiprocessing Nodes' [patent_app_type] => utility [patent_app_number] => 12/342660 [patent_app_country] => US [patent_app_date] => 2008-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 24983 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20100161938.pdf [firstpage_image] =>[orig_patent_app_number] => 12342660 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/342660
System-On-A-Chip Supporting A Networked Array Of Configurable Symmetric Multiprocessing Nodes Dec 22, 2008 Abandoned
Array ( [id] => 5587335 [patent_doc_number] => 20090106537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'PROCESSOR SUPPORTING VECTOR MODE EXECUTION' [patent_app_type] => utility [patent_app_number] => 12/341250 [patent_app_country] => US [patent_app_date] => 2008-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13659 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20090106537.pdf [firstpage_image] =>[orig_patent_app_number] => 12341250 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/341250
Replicating opcode to other lanes and modifying argument register to others in vector portion for parallel operation Dec 21, 2008 Issued
Array ( [id] => 8632904 [patent_doc_number] => 08365003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Synchronizing time domain signals in computing system using phase frequency slope value of cross power spectral density' [patent_app_type] => utility [patent_app_number] => 12/340239 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12340239 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/340239
Synchronizing time domain signals in computing system using phase frequency slope value of cross power spectral density Dec 18, 2008 Issued
Array ( [id] => 7681075 [patent_doc_number] => 20100023733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'Microprocessor Extended Instruction Set Precision Mode' [patent_app_type] => utility [patent_app_number] => 12/338972 [patent_app_country] => US [patent_app_date] => 2008-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5249 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20100023733.pdf [firstpage_image] =>[orig_patent_app_number] => 12338972 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/338972
Microprocessor Extended Instruction Set Precision Mode Dec 17, 2008 Abandoned
Array ( [id] => 5437780 [patent_doc_number] => 20090172367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'PROCESSING UNIT' [patent_app_type] => utility [patent_app_number] => 12/338245 [patent_app_country] => US [patent_app_date] => 2008-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10200 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20090172367.pdf [firstpage_image] =>[orig_patent_app_number] => 12338245 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/338245
Processor decoding extension instruction to store plural address extension information in extension register for plural subsequent instructions Dec 17, 2008 Issued
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