Jane J. Zara

Array ( [id] => 5339160 [patent_doc_number] => 20090055624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'CONTROL OF PROCESSING ELEMENTS IN PARALLEL PROCESSORS' [patent_app_type] => utility [patent_app_number] => 12/256328 [patent_app_country] => US [patent_app_date] => 2008-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7538 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20090055624.pdf [firstpage_image] =>[orig_patent_app_number] => 12256328 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6628583 [patent_doc_number] => 20100100707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'DATA STRUCTURE FOR CONTROLLING AN ALGORITHM PERFORMED ON A UNIT OF WORK IN A HIGHLY THREADED NETWORK ON A CHIP' [patent_app_type] => utility [patent_app_number] => 12/255827 [patent_app_country] => US [patent_app_date] => 2008-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20100100707.pdf [firstpage_image] =>[orig_patent_app_number] => 12255827 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7982605 [patent_doc_number] => 08074061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Executing micro-code instruction with delay field and address of next instruction which is decoded after indicated delay' [patent_app_type] => utility [patent_app_number] => 12/253339 [patent_app_country] => US [patent_app_date] => 2008-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4460 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/074/08074061.pdf [firstpage_image] =>[orig_patent_app_number] => 12253339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6628655 [patent_doc_number] => 20100100712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'Multi-Execution Unit Processing Unit with Instruction Blocking Sequencer Logic' [patent_app_type] => utility [patent_app_number] => 12/252541 [patent_app_country] => US [patent_app_date] => 2008-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11647 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20100100712.pdf [firstpage_image] =>[orig_patent_app_number] => 12252541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8623240 [patent_doc_number] => 08356161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-15 [patent_title] => 'Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements' [patent_app_type] => utility [patent_app_number] => 12/251946 [patent_app_country] => US [patent_app_date] => 2008-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 8521 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12251946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4443323 [patent_doc_number] => 07900025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations' [patent_app_type] => utility [patent_app_number] => 12/250575 [patent_app_country] => US [patent_app_date] => 2008-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 15403 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/900/07900025.pdf [firstpage_image] =>[orig_patent_app_number] => 12250575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4448941 [patent_doc_number] => 07865693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type' [patent_app_type] => utility [patent_app_number] => 12/250599 [patent_app_country] => US [patent_app_date] => 2008-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 15501 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865693.pdf [firstpage_image] =>[orig_patent_app_number] => 12250599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7706232 [patent_doc_number] => 08090929 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-03 [patent_title] => 'Generating clock signals for coupled ASIC chips in processor interface with X and Y logic operable in functional and scanning modes' [patent_app_type] => utility [patent_app_number] => 12/236551 [patent_app_country] => US [patent_app_date] => 2008-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/090/08090929.pdf [firstpage_image] =>[orig_patent_app_number] => 12236551 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5510312 [patent_doc_number] => 20090083519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'Processing Element (PE) Structure Forming Floating Point-Reconfigurable Array (FP-RA) and FP-RA Control Circuit for Controlling the FP-RA' [patent_app_type] => utility [patent_app_number] => 12/234507 [patent_app_country] => US [patent_app_date] => 2008-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9421 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20090083519.pdf [firstpage_image] =>[orig_patent_app_number] => 12234507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4614156 [patent_doc_number] => 07996661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Loop processing counter with automatic start time set or trigger modes in context reconfigurable PE array' [patent_app_type] => utility [patent_app_number] => 12/232462 [patent_app_country] => US [patent_app_date] => 2008-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6638 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/996/07996661.pdf [firstpage_image] =>[orig_patent_app_number] => 12232462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8183052 [patent_doc_number] => 08180998 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-15 [patent_title] => 'System of lanes of processing units receiving instructions via shared memory units for data-parallel or task-parallel operations' [patent_app_type] => utility [patent_app_number] => 12/208231 [patent_app_country] => US [patent_app_date] => 2008-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6818 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/180/08180998.pdf [firstpage_image] =>[orig_patent_app_number] => 12208231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5317625 [patent_doc_number] => 20090282223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'DATA PROCESSING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/204857 [patent_app_country] => US [patent_app_date] => 2008-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2381 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20090282223.pdf [firstpage_image] =>[orig_patent_app_number] => 12204857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4600624 [patent_doc_number] => 07984267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Message passing module in hybrid computing system starting and sending operation information to service program for accelerator to execute application program' [patent_app_type] => utility [patent_app_number] => 12/204352 [patent_app_country] => US [patent_app_date] => 2008-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14646 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/984/07984267.pdf [firstpage_image] =>[orig_patent_app_number] => 12204352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6227417 [patent_doc_number] => 20100057957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'RECONFIGURABLE FADEC FOR GAS TURBINE ENGINE' [patent_app_type] => utility [patent_app_number] => 12/201129 [patent_app_country] => US [patent_app_date] => 2008-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1977 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20100057957.pdf [firstpage_image] =>[orig_patent_app_number] => 12201129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5325832 [patent_doc_number] => 20090063822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'MICROPROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/200257 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3657 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20090063822.pdf [firstpage_image] =>[orig_patent_app_number] => 12200257 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5325837 [patent_doc_number] => 20090063827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'PARALLEL PROCESSOR AND ARITHMETIC METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 12/197663 [patent_app_country] => US [patent_app_date] => 2008-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20090063827.pdf [firstpage_image] =>[orig_patent_app_number] => 12197663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6617054 [patent_doc_number] => 20100049957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'RECOVERING A SUBORDINATE STRAND FROM A BRANCH MISPREDICTION USING STATE INFORMATION FROM A PRIMARY STRAND' [patent_app_type] => utility [patent_app_number] => 12/197629 [patent_app_country] => US [patent_app_date] => 2008-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5998 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20100049957.pdf [firstpage_image] =>[orig_patent_app_number] => 12197629 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4761207 [patent_doc_number] => 20080313433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'PROCESSOR FOR SIMULTANEOUSLY EXECUTING MULTIPLE CONDITIONAL EXECUTION INSTRUCTION GROUPS' [patent_app_type] => utility [patent_app_number] => 12/196102 [patent_app_country] => US [patent_app_date] => 2008-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12915 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313433.pdf [firstpage_image] =>[orig_patent_app_number] => 12196102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4761220 [patent_doc_number] => 20080313446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'PROCESSOR PREDICTING BRANCH FROM COMPRESSED ADDRESS INFORMATION' [patent_app_type] => utility [patent_app_number] => 12/195738 [patent_app_country] => US [patent_app_date] => 2008-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11198 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313446.pdf [firstpage_image] =>[orig_patent_app_number] => 12195738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4591987 [patent_doc_number] => 07836289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-16 [patent_title] => 'Branch predictor for setting predicate flag to skip predicated branch instruction execution in last iteration of loop processing' [patent_app_type] => utility [patent_app_number] => 12/194783 [patent_app_country] => US [patent_app_date] => 2008-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 8875 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/836/07836289.pdf [firstpage_image] =>[orig_patent_app_number] => 12194783 [rel_patent_id] =>[rel_patent_doc_number] =>)