Search

Janet L. Coppins

Examiner (ID: 16559, Phone: (571)272-0680 , Office: P/1672 )

Most Active Art Unit
1628
Art Unit(s)
1672, 1625, 1626, 1621, 1628
Total Applications
1618
Issued Applications
1050
Pending Applications
225
Abandoned Applications
373

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16637764 [patent_doc_number] => 10916278 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-09 [patent_title] => Memory controller and memory data receiving method for generate better sampling clock signal [patent_app_type] => utility [patent_app_number] => 16/575353 [patent_app_country] => US [patent_app_date] => 2019-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3241 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16575353 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/575353
Memory controller and memory data receiving method for generate better sampling clock signal Sep 17, 2019 Issued
Array ( [id] => 16119191 [patent_doc_number] => 20200211618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/570375 [patent_app_country] => US [patent_app_date] => 2019-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16570375 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/570375
Semiconductor devices for recognizing a phase of a division clock signal Sep 12, 2019 Issued
Array ( [id] => 16566637 [patent_doc_number] => 10892011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells [patent_app_type] => utility [patent_app_number] => 16/565967 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 69 [patent_figures_cnt] => 93 [patent_no_of_words] => 100167 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16565967 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/565967
Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells Sep 9, 2019 Issued
Array ( [id] => 16301190 [patent_doc_number] => 20200286913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/564673 [patent_app_country] => US [patent_app_date] => 2019-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16564673 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/564673
Semiconductor device including a passivation film and multiple word lines Sep 8, 2019 Issued
Array ( [id] => 16315841 [patent_doc_number] => 20200294579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/555805 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4545 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16555805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/555805
Semiconductor storage device with assist timing control circuit Aug 28, 2019 Issued
Array ( [id] => 16773734 [patent_doc_number] => 10984852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Sensing operations in memory by comparing inputs in a sense amplifier [patent_app_type] => utility [patent_app_number] => 16/553846 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5471 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553846 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/553846
Sensing operations in memory by comparing inputs in a sense amplifier Aug 27, 2019 Issued
Array ( [id] => 15259651 [patent_doc_number] => 20190378559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => APPARATUSES AND METHODS FOR CONCENTRATED ARRANGEMENT OF AMPLIFIERS [patent_app_type] => utility [patent_app_number] => 16/551612 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16551612 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/551612
Apparatuses and methods for concentrated arrangement of amplifiers Aug 25, 2019 Issued
Array ( [id] => 15562471 [patent_doc_number] => 20200065647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => ARTIFICIAL NEURON BASED ON FERROELECTRIC CIRCUIT ELEMENT [patent_app_type] => utility [patent_app_number] => 16/550515 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550515 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/550515
Artificial neuron based on ferroelectric circuit element Aug 25, 2019 Issued
Array ( [id] => 15597061 [patent_doc_number] => 20200075065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => BIT LINE SENSE AMPLIFIER CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/545805 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16545805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/545805
Bit line sense amplifier circuit capable of reducing offset voltage Aug 19, 2019 Issued
Array ( [id] => 16386234 [patent_doc_number] => 10811075 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-20 [patent_title] => Method for performing access control regarding quality of service optimization of memory device with aid of machine learning, associated memory device and controller thereof [patent_app_type] => utility [patent_app_number] => 16/543639 [patent_app_country] => US [patent_app_date] => 2019-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13891 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16543639 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/543639
Method for performing access control regarding quality of service optimization of memory device with aid of machine learning, associated memory device and controller thereof Aug 18, 2019 Issued
Array ( [id] => 15440233 [patent_doc_number] => 20200034300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => CONTINUOUS PAGE READ FOR MEMORY [patent_app_type] => utility [patent_app_number] => 16/537151 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16537151 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/537151
Uninterrupted read of consecutive pages for memory Aug 8, 2019 Issued
Array ( [id] => 16684160 [patent_doc_number] => 10943649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Apparatus and method for controlling gradual conductance change in synaptic element [patent_app_type] => utility [patent_app_number] => 16/526331 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6370 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526331 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526331
Apparatus and method for controlling gradual conductance change in synaptic element Jul 29, 2019 Issued
Array ( [id] => 15153891 [patent_doc_number] => 20190355423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => PROGRAMMING OF MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/525804 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6835 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16525804 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/525804
Programming of memory devices in response to programming voltages indicative of programming efficiency Jul 29, 2019 Issued
Array ( [id] => 16574778 [patent_doc_number] => 10896703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Memory device with an input signal management mechanism [patent_app_type] => utility [patent_app_number] => 16/523952 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523952 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523952
Memory device with an input signal management mechanism Jul 25, 2019 Issued
Array ( [id] => 16566621 [patent_doc_number] => 10891995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Command generation method and semiconductor device related to the command generation method [patent_app_type] => utility [patent_app_number] => 16/518635 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7580 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16518635 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/518635
Command generation method and semiconductor device related to the command generation method Jul 21, 2019 Issued
Array ( [id] => 16464216 [patent_doc_number] => 10847579 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-24 [patent_title] => Method for fabricating an array of 4F2 resistive non-volatile memory in a NAND architecture [patent_app_type] => utility [patent_app_number] => 16/518234 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14688 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16518234 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/518234
Method for fabricating an array of 4F2 resistive non-volatile memory in a NAND architecture Jul 21, 2019 Issued
Array ( [id] => 16585820 [patent_doc_number] => 20210020222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => FERROELECTRIC MEMORY CELL WITH ACCESS LINE DISTURBANCE MITIGATION [patent_app_type] => utility [patent_app_number] => 16/514481 [patent_app_country] => US [patent_app_date] => 2019-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21324 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16514481 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/514481
Ferroelectric memory cell with access line disturbance mitigation Jul 16, 2019 Issued
Array ( [id] => 15092579 [patent_doc_number] => 20190341101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => FULL-SWING DUAL-RAIL SRAM SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 16/512133 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16512133 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/512133
Full-swing dual-rail SRAM sense amplifier Jul 14, 2019 Issued
Array ( [id] => 16119255 [patent_doc_number] => 20200211650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => MEMORY DEVICE HAVING IMPROVED PROGRAM AND ERASE OPERATIONS AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/510071 [patent_app_country] => US [patent_app_date] => 2019-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16510071 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/510071
Memory device having improved program and erase operations and operating method of the memory device Jul 11, 2019 Issued
Array ( [id] => 16249227 [patent_doc_number] => 10748599 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-18 [patent_title] => Data reading method, storage controller and storage device background of the disclosure [patent_app_type] => utility [patent_app_number] => 16/503637 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 18158 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503637 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503637
Data reading method, storage controller and storage device background of the disclosure Jul 4, 2019 Issued
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