Search

Jany Richardson

Examiner (ID: 7533, Phone: (571)270-5074 , Office: P/2844 )

Most Active Art Unit
2844
Art Unit(s)
2819, 2844, 2845, 4125
Total Applications
1293
Issued Applications
1166
Pending Applications
48
Abandoned Applications
94

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20291904 [patent_doc_number] => 20250317147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => CONTROLLING AND POWERING MULTIPLE CHIPS [patent_app_type] => utility [patent_app_number] => 19/242181 [patent_app_country] => US [patent_app_date] => 2025-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7113 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19242181 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/242181
Controlling and powering multiple chips Jun 17, 2025 Issued
Array ( [id] => 20089706 [patent_doc_number] => 20250219642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => MEMORY MODULE WITH FINE-GRAINED VOLTAGE ADJUSTMENT CAPABILITIES [patent_app_type] => utility [patent_app_number] => 19/081957 [patent_app_country] => US [patent_app_date] => 2025-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19081957 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/081957
MEMORY MODULE WITH FINE-GRAINED VOLTAGE ADJUSTMENT CAPABILITIES Mar 16, 2025 Pending
Array ( [id] => 20660986 [patent_doc_number] => 20260113040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-23 [patent_title] => CELL REGION HAVING THREE-STATE INVERTING CIRCUIT COUPLED BETWEEN A REFERENCE VOLTAGE AND A NON-REFERENCE-VOLTAGE SIGNAL AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 19/047221 [patent_app_country] => US [patent_app_date] => 2025-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19047221 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/047221
CELL REGION HAVING THREE-STATE INVERTING CIRCUIT COUPLED BETWEEN A REFERENCE VOLTAGE AND A NON-REFERENCE-VOLTAGE SIGNAL AND METHOD OF MANUFACTURING SAME Feb 5, 2025 Pending
Array ( [id] => 19972889 [patent_doc_number] => 12341514 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-24 [patent_title] => Controlling and powering multiple chips [patent_app_type] => utility [patent_app_number] => 19/035308 [patent_app_country] => US [patent_app_date] => 2025-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7104 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19035308 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/035308
Controlling and powering multiple chips Jan 22, 2025 Issued
Array ( [id] => 20287904 [patent_doc_number] => 20250313147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-09 [patent_title] => LAMP CONTROL SYSTEM, LAMP CONTROL METHOD, AND VEHICLE [patent_app_type] => utility [patent_app_number] => 19/034239 [patent_app_country] => US [patent_app_date] => 2025-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19034239 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/034239
LAMP CONTROL SYSTEM, LAMP CONTROL METHOD, AND VEHICLE Jan 21, 2025 Pending
Array ( [id] => 20021558 [patent_doc_number] => 20250159780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => MONITORING APPARATUS AND SYSTEM [patent_app_type] => utility [patent_app_number] => 19/028315 [patent_app_country] => US [patent_app_date] => 2025-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19028315 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/028315
MONITORING APPARATUS AND SYSTEM Jan 16, 2025 Pending
Array ( [id] => 20011861 [patent_doc_number] => 20250150083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 19/018549 [patent_app_country] => US [patent_app_date] => 2025-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19018549 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/018549
SEMICONDUCTOR DEVICE Jan 12, 2025 Pending
Array ( [id] => 20096892 [patent_doc_number] => 20250226828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => CONTROL DEVICE AND IMAGE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 19/011946 [patent_app_country] => US [patent_app_date] => 2025-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19011946 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/011946
CONTROL DEVICE AND IMAGE PROCESSING APPARATUS Jan 6, 2025 Pending
Array ( [id] => 20103654 [patent_doc_number] => 20250233590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => OUTPUT DRIVER AND OUTPUT BUFFER CIRCUIT INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 19/010480 [patent_app_country] => US [patent_app_date] => 2025-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19010480 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/010480
OUTPUT DRIVER AND OUTPUT BUFFER CIRCUIT INCLUDING THE SAME Jan 5, 2025 Pending
Array ( [id] => 20558872 [patent_doc_number] => 20260058659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-26 [patent_title] => CIRCUIT WITH CALIBRATION FUNCTION AND CIRCUIT CALIBRATION METHOD [patent_app_type] => utility [patent_app_number] => 19/006144 [patent_app_country] => US [patent_app_date] => 2024-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19006144 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/006144
CIRCUIT WITH CALIBRATION FUNCTION AND CIRCUIT CALIBRATION METHOD Dec 29, 2024 Pending
Array ( [id] => 20806683 [patent_doc_number] => 12671598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-30 [patent_title] => Strong PUF circuit with good stability and anti-ML attack capacity [patent_app_type] => utility [patent_app_number] => 18/981643 [patent_app_country] => US [patent_app_date] => 2024-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4021 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 911 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18981643 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/981643
STRONG PUF CIRCUIT WITH GOOD STABILITY AND ANTI-ML ATTACK CAPACITY Dec 15, 2024 Issued
Array ( [id] => 20052167 [patent_doc_number] => 20250190389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => CONTROLLER AREA NETWORK (CAN) BUS DRIVER USING TRANSLINEAR LOOPS [patent_app_type] => utility [patent_app_number] => 18/977300 [patent_app_country] => US [patent_app_date] => 2024-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18977300 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/977300
CONTROLLER AREA NETWORK (CAN) BUS DRIVER USING TRANSLINEAR LOOPS Dec 10, 2024 Pending
Array ( [id] => 20021998 [patent_doc_number] => 20250160220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => FLEXIBLE WIRING FOR LOW TEMPERATURE APPLICATIONS [patent_app_type] => utility [patent_app_number] => 18/958863 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7367 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18958863 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/958863
FLEXIBLE WIRING FOR LOW TEMPERATURE APPLICATIONS Nov 24, 2024 Pending
Array ( [id] => 20724074 [patent_doc_number] => 20260140787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-21 [patent_title] => Reversible Logic Gate-Based Thermal Management with Dedicated Entropy Offloading Unit for High-Performance Processor [patent_app_type] => utility [patent_app_number] => 18/951895 [patent_app_country] => US [patent_app_date] => 2024-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18951895 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/951895
Reversible Logic Gate-Based Thermal Management with Dedicated Entropy Offloading Unit for High-Performance Processor Nov 18, 2024 Pending
Array ( [id] => 20063574 [patent_doc_number] => 20250201796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => MEMORY CHIP, LOGIC CHIP, CHIP-STACKED STRUCTURE, AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/943754 [patent_app_country] => US [patent_app_date] => 2024-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18943754 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/943754
MEMORY CHIP, LOGIC CHIP, CHIP-STACKED STRUCTURE, AND MEMORY Nov 10, 2024 Pending
Array ( [id] => 20003212 [patent_doc_number] => 20250141434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => METHODS AND CIRCUITS FOR SLEW-RATE CALIBRATION [patent_app_type] => utility [patent_app_number] => 18/939768 [patent_app_country] => US [patent_app_date] => 2024-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18939768 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/939768
METHODS AND CIRCUITS FOR SLEW-RATE CALIBRATION Nov 6, 2024 Pending
Array ( [id] => 20814074 [patent_doc_number] => 20260188908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-07-02 [patent_title] => COMMUNICATION DEVICE [patent_app_type] => utility [patent_app_number] => 18/860752 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18860752 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/860752
COMMUNICATION DEVICE Oct 27, 2024 Pending
Array ( [id] => 20353413 [patent_doc_number] => 20250350265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => ELECTRONIC DEVICE COMMUNICATING WITH EXTERNAL DEVICE, OPERATING METHOD OF ELECTRONIC DEVICE, AND ELECTRONIC SYSTEM INCLUDING ELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 18/924695 [patent_app_country] => US [patent_app_date] => 2024-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4694 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18924695 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/924695
ELECTRONIC DEVICE COMMUNICATING WITH EXTERNAL DEVICE, OPERATING METHOD OF ELECTRONIC DEVICE, AND ELECTRONIC SYSTEM INCLUDING ELECTRONIC DEVICES Oct 22, 2024 Pending
Array ( [id] => 19728541 [patent_doc_number] => 20250031292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => LIGHTING LOAD CLASSIFICATION AND DIMMER CONFIGURATION BASED THEREON [patent_app_type] => utility [patent_app_number] => 18/904538 [patent_app_country] => US [patent_app_date] => 2024-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18904538 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/904538
LIGHTING LOAD CLASSIFICATION AND DIMMER CONFIGURATION BASED THEREON Oct 1, 2024 Pending
Array ( [id] => 20631695 [patent_doc_number] => 20260095985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-02 [patent_title] => CIRCUITS FOR DISTRIBUTING BITMAPS FOR A PLURALITY OF PIXELATED LIGHT SOURCES [patent_app_type] => utility [patent_app_number] => 18/900190 [patent_app_country] => US [patent_app_date] => 2024-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18900190 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/900190
CIRCUITS FOR DISTRIBUTING BITMAPS FOR A PLURALITY OF PIXELATED LIGHT SOURCES Sep 26, 2024 Pending
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