Search

Jarrett J. Stark

Examiner (ID: 14467, Phone: (571)272-6005 , Office: P/2823 )

Most Active Art Unit
2823
Art Unit(s)
2898, 2823, 2822
Total Applications
1751
Issued Applications
1172
Pending Applications
156
Abandoned Applications
451

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18205398 [patent_doc_number] => 11587802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Semiconductor fabrication tool having gas manifold assembled by jig [patent_app_type] => utility [patent_app_number] => 16/749286 [patent_app_country] => US [patent_app_date] => 2020-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 7328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16749286 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/749286
Semiconductor fabrication tool having gas manifold assembled by jig Jan 21, 2020 Issued
Array ( [id] => 15906105 [patent_doc_number] => 20200152573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE OF THREE-DIMENSIONAL STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/747171 [patent_app_country] => US [patent_app_date] => 2020-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11971 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747171 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747171
Semiconductor memory device of three-dimensional structure Jan 19, 2020 Issued
Array ( [id] => 15906469 [patent_doc_number] => 20200152755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => VERTICAL FIN-TYPE BIPOLAR JUNCTION TRANSISTOR WITH SELF-ALIGNED BASE CONTACT [patent_app_type] => utility [patent_app_number] => 16/745148 [patent_app_country] => US [patent_app_date] => 2020-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16745148 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/745148
Vertical fin-type bipolar junction transistor with self-aligned base contact Jan 15, 2020 Issued
Array ( [id] => 16080699 [patent_doc_number] => 20200194336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => HIGH POWER MODULE SEMICONDUCTOR PACKAGE WITH MULTIPLE SUBMODULES [patent_app_type] => utility [patent_app_number] => 16/732192 [patent_app_country] => US [patent_app_date] => 2019-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732192 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/732192
High power module semiconductor package with multiple submodules Dec 30, 2019 Issued
Array ( [id] => 15865711 [patent_doc_number] => 20200140259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => METHOD OF FORMING SEMICONDUCTOR DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/731183 [patent_app_country] => US [patent_app_date] => 2019-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16731183 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/731183
Method of forming semiconductor device structure Dec 30, 2019 Issued
Array ( [id] => 16936664 [patent_doc_number] => 20210202553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => IMAGE SENSOR WITH FULLY DEPLETED SILICON ON INSULATOR SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/730756 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16730756 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/730756
Image sensor with fully depleted silicon on insulator substrate Dec 29, 2019 Issued
Array ( [id] => 17652647 [patent_doc_number] => 11355387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Semiconductor device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 16/730367 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 6049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16730367 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/730367
Semiconductor device and method of fabricating the same Dec 29, 2019 Issued
Array ( [id] => 16936583 [patent_doc_number] => 20210202472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => INTEGRATED CIRCUIT STRUCTURES INCLUDING BACKSIDE VIAS [patent_app_type] => utility [patent_app_number] => 16/728111 [patent_app_country] => US [patent_app_date] => 2019-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728111 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/728111
INTEGRATED CIRCUIT STRUCTURES INCLUDING BACKSIDE VIAS Dec 26, 2019 Abandoned
Array ( [id] => 16120473 [patent_doc_number] => 20200212259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => SEMICONDUCTOR STACK, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/728769 [patent_app_country] => US [patent_app_date] => 2019-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728769 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/728769
Semiconductor stack, semiconductor device and method for manufacturing the same Dec 26, 2019 Issued
Array ( [id] => 15873607 [patent_doc_number] => 20200144207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/723041 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723041 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/723041
Semiconductor structure and manufacturing method thereof Dec 19, 2019 Issued
Array ( [id] => 19342716 [patent_doc_number] => 12052924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Method and system for fabricating a piezoelectric device [patent_app_type] => utility [patent_app_number] => 16/723363 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 7245 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723363 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/723363
Method and system for fabricating a piezoelectric device Dec 19, 2019 Issued
Array ( [id] => 16920831 [patent_doc_number] => 20210193923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => RESISTIVE RANDOM ACCESS MEMORY CELLS INTEGRATED WITH VERTICAL FIELD EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 16/723217 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16723217 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/723217
Resistive random access memory cells integrated with vertical field effect transistor Dec 19, 2019 Issued
Array ( [id] => 17862898 [patent_doc_number] => 11444059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Wafer-level stacked die structures and associated systems and methods [patent_app_type] => utility [patent_app_number] => 16/721670 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 4504 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721670 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/721670
Wafer-level stacked die structures and associated systems and methods Dec 18, 2019 Issued
Array ( [id] => 16920410 [patent_doc_number] => 20210193502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => METHOD OF PROCESSING WAFER [patent_app_type] => utility [patent_app_number] => 16/718506 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5997 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16718506 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/718506
Method of processing wafer Dec 17, 2019 Issued
Array ( [id] => 17486306 [patent_doc_number] => 20220093810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => DEVICES COMPRISING MULTIPLE TWO-DIMENSIONAL TRANSITION METAL DICHALCOGENIDE MATERIALS [patent_app_type] => utility [patent_app_number] => 17/413927 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17413927 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/413927
DEVICES COMPRISING MULTIPLE TWO-DIMENSIONAL TRANSITION METAL DICHALCOGENIDE MATERIALS Dec 15, 2019 Abandoned
Array ( [id] => 16020771 [patent_doc_number] => 20200185229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => ETCHING METHOD AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 16/704129 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704129 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704129
Etching method and substrate processing apparatus Dec 4, 2019 Issued
Array ( [id] => 18120840 [patent_doc_number] => 11552239 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Superconducting qubit and resonator system based on the Josephson ring modulator [patent_app_type] => utility [patent_app_number] => 16/698216 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16698216 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/698216
Superconducting qubit and resonator system based on the Josephson ring modulator Nov 26, 2019 Issued
Array ( [id] => 17745773 [patent_doc_number] => 11393855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Photoelectric conversion apparatus, photoelectric conversion system, and moving object [patent_app_type] => utility [patent_app_number] => 16/693114 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 32 [patent_no_of_words] => 8597 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16693114 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/693114
Photoelectric conversion apparatus, photoelectric conversion system, and moving object Nov 21, 2019 Issued
Array ( [id] => 17607184 [patent_doc_number] => 11335676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/692992 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7105 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692992 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692992
Semiconductor device Nov 21, 2019 Issued
Array ( [id] => 20376875 [patent_doc_number] => 12484333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Shingled solar cell panel and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/631166 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 4610 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17631166 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/631166
Shingled solar cell panel and method of manufacturing the same Nov 17, 2019 Issued
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