Jasmine Jhihan B. Clark

Array ( [id] => 20089106 [patent_doc_number] => 20250219042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => HIGH BANDWIDTH MEMORY STACK WITH SIDE EDGE INTERCONNECTION AND 3D IC STRUCTURE WITH THE SAME [patent_app_type] => utility [patent_app_number] => 19/062467 [patent_app_country] => US [patent_app_date] => 2025-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19062467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19688169 [patent_doc_number] => 20250006714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/762255 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18762255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20733066 [patent_doc_number] => 12640326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Systems and methods for fabricating silicon die stacks for electron emitter array chips [patent_app_type] => utility [patent_app_number] => 18/760072 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20089099 [patent_doc_number] => 20250219035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/751086 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20089100 [patent_doc_number] => 20250219036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => ELECTRICAL INTERCONNECTS FOR PACKAGES CONTAINING PHOTONIC INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/751101 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13005 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19515749 [patent_doc_number] => 20240347435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING UNDER BUMP METALLIZATION PAD [patent_app_type] => utility [patent_app_number] => 18/748765 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5007 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18748765 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19484201 [patent_doc_number] => 20240332243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => PACKAGES WITH ELECTRICAL FUSES [patent_app_type] => utility [patent_app_number] => 18/740456 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740456 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19452960 [patent_doc_number] => 20240313090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => MULTI-GATE DEVICE FABRICATION AND STRUCTURES THEREOF [patent_app_type] => utility [patent_app_number] => 18/674285 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19654464 [patent_doc_number] => 12176264 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-12-24 [patent_title] => Manifold designs for embedded liquid cooling in a package [patent_app_type] => utility [patent_app_number] => 18/674581 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15853 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20496910 [patent_doc_number] => 12538804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Integrated circuit packages to minimize stress on a semiconductor die [patent_app_type] => utility [patent_app_number] => 18/670309 [patent_app_country] => US [patent_app_date] => 2024-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 21328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18670309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19421017 [patent_doc_number] => 20240297141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING NON-CONDUCTIVE FILM AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/659400 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11742 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659400 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20229343 [patent_doc_number] => 12417999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-16 [patent_title] => Semiconductor packages using package in package systems and related methods [patent_app_type] => utility [patent_app_number] => 18/632548 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 1134 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632548 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19941759 [patent_doc_number] => 12313886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Data processing systems including optical communication modules [patent_app_type] => utility [patent_app_number] => 18/617137 [patent_app_country] => US [patent_app_date] => 2024-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 168 [patent_figures_cnt] => 217 [patent_no_of_words] => 115503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18617137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19349279 [patent_doc_number] => 20240258243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => STACKED DIE MODULES FOR SEMICONDUCTOR DEVICE ASSEMBLIES AND METHODS OF MANUFACTURING STACKED DIE MODULES [patent_app_type] => utility [patent_app_number] => 18/614579 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19237379 [patent_doc_number] => 20240194574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => PROCESS FOR THIN FILM CAPACITOR INTEGRATION [patent_app_type] => utility [patent_app_number] => 18/585629 [patent_app_country] => US [patent_app_date] => 2024-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3337 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18585629 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19221590 [patent_doc_number] => 20240186294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => SEMICONDUCTOR PACKAGE INCLUDING PLURALITY OF SEMICONDUCTOR CHIPS AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/438658 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11581 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19206276 [patent_doc_number] => 20240178175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => UNIFORM ELECTROCHEMICAL PLATING OF METAL ONTO ARRAYS OF PILLARS HAVING DIFFERENT LATERAL DENSITIES AND RELATED TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 18/435628 [patent_app_country] => US [patent_app_date] => 2024-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18435628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20267129 [patent_doc_number] => 12438128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Semiconductor device package [patent_app_type] => utility [patent_app_number] => 18/426124 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 1023 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426124 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20375347 [patent_doc_number] => 12482791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Stacked integrated circuits with redistribution lines [patent_app_type] => utility [patent_app_number] => 18/425936 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 989 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20389327 [patent_doc_number] => 12489062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Semiconductor package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/423166 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 3166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423166 [rel_patent_id] =>[rel_patent_doc_number] =>)