Jasmine Jhihan B. Clark

Array ( [id] => 7273082 [patent_doc_number] => 20040232533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Semiconductor apparatus and fabricating method for the same' [patent_app_type] => new [patent_app_number] => 10/819801 [patent_app_country] => US [patent_app_date] => 2004-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20040232533.pdf [firstpage_image] =>[orig_patent_app_number] => 10819801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 972116 [patent_doc_number] => 06936501 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-30 [patent_title] => 'Semiconductor component and method of manufacture' [patent_app_type] => utility [patent_app_number] => 10/818981 [patent_app_country] => US [patent_app_date] => 2004-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2468 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/936/06936501.pdf [firstpage_image] =>[orig_patent_app_number] => 10818981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7421263 [patent_doc_number] => 20040183183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Integrated circuit stacking system and method' [patent_app_type] => new [patent_app_number] => 10/814532 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 11765 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20040183183.pdf [firstpage_image] =>[orig_patent_app_number] => 10814532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 751981 [patent_doc_number] => 07023089 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-04 [patent_title] => 'Low temperature packaging apparatus and method' [patent_app_type] => utility [patent_app_number] => 10/814212 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5242 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023089.pdf [firstpage_image] =>[orig_patent_app_number] => 10814212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7375719 [patent_doc_number] => 20040178511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Method of attaching a die to a substrate' [patent_app_type] => new [patent_app_number] => 10/811581 [patent_app_country] => US [patent_app_date] => 2004-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2868 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20040178511.pdf [firstpage_image] =>[orig_patent_app_number] => 10811581 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 979392 [patent_doc_number] => 06930398 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-16 [patent_title] => 'Package structure for optical image sensing integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/708761 [patent_app_country] => US [patent_app_date] => 2004-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1406 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930398.pdf [firstpage_image] =>[orig_patent_app_number] => 10708761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6955735 [patent_doc_number] => 20050212105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Integrated circuit die and substrate coupling' [patent_app_type] => utility [patent_app_number] => 10/807022 [patent_app_country] => US [patent_app_date] => 2004-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2184 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20050212105.pdf [firstpage_image] =>[orig_patent_app_number] => 10807022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7314374 [patent_doc_number] => 20040222530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'Semiconductor device having low-k dielectric film in pad region and method for manufacturing thereof' [patent_app_type] => new [patent_app_number] => 10/806341 [patent_app_country] => US [patent_app_date] => 2004-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2344 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20040222530.pdf [firstpage_image] =>[orig_patent_app_number] => 10806341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1022612 [patent_doc_number] => 06888253 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-03 [patent_title] => 'Inexpensive wafer level MMIC chip packaging' [patent_app_type] => utility [patent_app_number] => 10/799062 [patent_app_country] => US [patent_app_date] => 2004-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 4937 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/888/06888253.pdf [firstpage_image] =>[orig_patent_app_number] => 10799062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7375575 [patent_doc_number] => 20040178487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Electronic circuit unit that is easy to manufacture and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/796632 [patent_app_country] => US [patent_app_date] => 2004-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3088 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20040178487.pdf [firstpage_image] =>[orig_patent_app_number] => 10796632 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 941515 [patent_doc_number] => 06969906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-29 [patent_title] => 'Multi-chip package and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/787499 [patent_app_country] => US [patent_app_date] => 2004-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 5429 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/969/06969906.pdf [firstpage_image] =>[orig_patent_app_number] => 10787499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 734379 [patent_doc_number] => 07038327 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-02 [patent_title] => 'Anisotropic conductive film bonding pad' [patent_app_type] => utility [patent_app_number] => 10/787801 [patent_app_country] => US [patent_app_date] => 2004-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 2702 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/038/07038327.pdf [firstpage_image] =>[orig_patent_app_number] => 10787801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 687885 [patent_doc_number] => 07078823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Semiconductor die configured for use with interposer substrates having reinforced interconnect slots' [patent_app_type] => utility [patent_app_number] => 10/787351 [patent_app_country] => US [patent_app_date] => 2004-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4406 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/078/07078823.pdf [firstpage_image] =>[orig_patent_app_number] => 10787351 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7415353 [patent_doc_number] => 20040159957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Interposer substrate and wafer scale interposer substrate member for use with flip-chip configured semiconductor dice' [patent_app_type] => new [patent_app_number] => 10/782270 [patent_app_country] => US [patent_app_date] => 2004-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13039 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20040159957.pdf [firstpage_image] =>[orig_patent_app_number] => 10782270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1069247 [patent_doc_number] => 06844615 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-18 [patent_title] => 'Leadframe package for semiconductor devices' [patent_app_type] => utility [patent_app_number] => 10/781220 [patent_app_country] => US [patent_app_date] => 2004-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6573 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/844/06844615.pdf [firstpage_image] =>[orig_patent_app_number] => 10781220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 356583 [patent_doc_number] => 07489021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Lead frame with included passive devices' [patent_app_type] => utility [patent_app_number] => 10/563172 [patent_app_country] => US [patent_app_date] => 2004-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4558 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/489/07489021.pdf [firstpage_image] =>[orig_patent_app_number] => 10563172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5916692 [patent_doc_number] => 20060237838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Thermal interconnect systems methods of production and uses thereof' [patent_app_type] => utility [patent_app_number] => 10/545597 [patent_app_country] => US [patent_app_date] => 2004-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4764 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20060237838.pdf [firstpage_image] =>[orig_patent_app_number] => 10545597 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7415241 [patent_doc_number] => 20040159942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Semiconductor package and method producing same' [patent_app_type] => new [patent_app_number] => 10/777582 [patent_app_country] => US [patent_app_date] => 2004-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5181 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20040159942.pdf [firstpage_image] =>[orig_patent_app_number] => 10777582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 938663 [patent_doc_number] => 06972492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-06 [patent_title] => 'Method and structure to form capacitor in copper damascene process for integrated circuit devices' [patent_app_type] => utility [patent_app_number] => 10/773592 [patent_app_country] => US [patent_app_date] => 2004-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2883 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972492.pdf [firstpage_image] =>[orig_patent_app_number] => 10773592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5848746 [patent_doc_number] => 20060231937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Thin multiple semiconductor die package' [patent_app_type] => utility [patent_app_number] => 10/542211 [patent_app_country] => US [patent_app_date] => 2004-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3800 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20060231937.pdf [firstpage_image] =>[orig_patent_app_number] => 10542211 [rel_patent_id] =>[rel_patent_doc_number] =>)