Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7301225 [patent_doc_number] => 20040113202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses' [patent_app_type] => new [patent_app_number] => 10/640742 [patent_app_country] => US [patent_app_date] => 2003-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4850 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20040113202.pdf [firstpage_image] =>[orig_patent_app_number] => 10640742 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/640742
Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses Aug 13, 2003 Issued
Array ( [id] => 1069253 [patent_doc_number] => 06844621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-18 [patent_title] => 'Semiconductor device and method of relaxing thermal stress' [patent_app_type] => utility [patent_app_number] => 10/640182 [patent_app_country] => US [patent_app_date] => 2003-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 7832 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/844/06844621.pdf [firstpage_image] =>[orig_patent_app_number] => 10640182 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/640182
Semiconductor device and method of relaxing thermal stress Aug 12, 2003 Issued
Array ( [id] => 1060191 [patent_doc_number] => 06853069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'Packaged die on PCB with heat sink encapsulant and methods' [patent_app_type] => utility [patent_app_number] => 10/639349 [patent_app_country] => US [patent_app_date] => 2003-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3211 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/853/06853069.pdf [firstpage_image] =>[orig_patent_app_number] => 10639349 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/639349
Packaged die on PCB with heat sink encapsulant and methods Aug 11, 2003 Issued
Array ( [id] => 1068694 [patent_doc_number] => 06844220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-18 [patent_title] => 'Multilayer ceramic electronic component, electronic component aggregate, and method for producing multilayer ceramic electronic component' [patent_app_type] => utility [patent_app_number] => 10/637632 [patent_app_country] => US [patent_app_date] => 2003-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5625 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/844/06844220.pdf [firstpage_image] =>[orig_patent_app_number] => 10637632 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/637632
Multilayer ceramic electronic component, electronic component aggregate, and method for producing multilayer ceramic electronic component Aug 10, 2003 Issued
Array ( [id] => 1053805 [patent_doc_number] => 06858930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-22 [patent_title] => 'Multi chip module' [patent_app_type] => utility [patent_app_number] => 10/638772 [patent_app_country] => US [patent_app_date] => 2003-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2040 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/858/06858930.pdf [firstpage_image] =>[orig_patent_app_number] => 10638772 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/638772
Multi chip module Aug 10, 2003 Issued
Array ( [id] => 7368838 [patent_doc_number] => 20040026767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Wiring substrate having position information' [patent_app_type] => new [patent_app_number] => 10/637552 [patent_app_country] => US [patent_app_date] => 2003-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9383 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20040026767.pdf [firstpage_image] =>[orig_patent_app_number] => 10637552 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/637552
Wiring substrate having position information Aug 10, 2003 Issued
Array ( [id] => 774884 [patent_doc_number] => 07002254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Integrated circuit package employing flip-chip technology and method of assembly' [patent_app_type] => utility [patent_app_number] => 10/636993 [patent_app_country] => US [patent_app_date] => 2003-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 45 [patent_no_of_words] => 5273 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/002/07002254.pdf [firstpage_image] =>[orig_patent_app_number] => 10636993 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/636993
Integrated circuit package employing flip-chip technology and method of assembly Aug 5, 2003 Issued
Array ( [id] => 7368994 [patent_doc_number] => 20040026795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Five layer adhesive/insulator/metal/insulator/adhesive tape for semiconductor die packaging' [patent_app_type] => new [patent_app_number] => 10/633752 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2003 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20040026795.pdf [firstpage_image] =>[orig_patent_app_number] => 10633752 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/633752
Five layer adhesive/insulator/metal/insulator/adhesive tape for semiconductor die packaging Aug 3, 2003 Issued
Array ( [id] => 1074096 [patent_doc_number] => 06838761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield' [patent_app_type] => utility [patent_app_number] => 10/632551 [patent_app_country] => US [patent_app_date] => 2003-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 21696 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838761.pdf [firstpage_image] =>[orig_patent_app_number] => 10632551 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/632551
Semiconductor multi-package module having wire bond interconnect between stacked packages and having electrical shield Aug 1, 2003 Issued
Array ( [id] => 7456334 [patent_doc_number] => 20040119070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Integrated microchip design' [patent_app_type] => new [patent_app_number] => 10/633171 [patent_app_country] => US [patent_app_date] => 2003-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20040119070.pdf [firstpage_image] =>[orig_patent_app_number] => 10633171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/633171
Integrated microchip design Jul 31, 2003 Issued
Array ( [id] => 7148053 [patent_doc_number] => 20050023705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Power grid layout techniques on integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/631471 [patent_app_country] => US [patent_app_date] => 2003-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3825 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20050023705.pdf [firstpage_image] =>[orig_patent_app_number] => 10631471 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/631471
Power grid layout techniques on integrated circuits Jul 29, 2003 Issued
Array ( [id] => 7448389 [patent_doc_number] => 20040164391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Stacked semiconductor device' [patent_app_type] => new [patent_app_number] => 10/626882 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3092 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20040164391.pdf [firstpage_image] =>[orig_patent_app_number] => 10626882 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/626882
Stacked semiconductor device Jul 24, 2003 Abandoned
Array ( [id] => 1074089 [patent_doc_number] => 06838754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Multi-chip package' [patent_app_type] => utility [patent_app_number] => 10/621581 [patent_app_country] => US [patent_app_date] => 2003-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 5256 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838754.pdf [firstpage_image] =>[orig_patent_app_number] => 10621581 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/621581
Multi-chip package Jul 17, 2003 Issued
Array ( [id] => 1025611 [patent_doc_number] => 06885109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-26 [patent_title] => 'Semiconductor device having a step-like section on the back side of the substrate, and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/621561 [patent_app_country] => US [patent_app_date] => 2003-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 52 [patent_no_of_words] => 8734 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/885/06885109.pdf [firstpage_image] =>[orig_patent_app_number] => 10621561 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/621561
Semiconductor device having a step-like section on the back side of the substrate, and method for manufacturing the same Jul 17, 2003 Issued
Array ( [id] => 1006133 [patent_doc_number] => 06906429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/619551 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 24 [patent_no_of_words] => 7253 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906429.pdf [firstpage_image] =>[orig_patent_app_number] => 10619551 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/619551
Semiconductor device and method of fabricating the same Jul 15, 2003 Issued
Array ( [id] => 7348399 [patent_doc_number] => 20040012088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Semiconductor device having a ball grid array and a fabrication process thereof' [patent_app_type] => new [patent_app_number] => 10/618721 [patent_app_country] => US [patent_app_date] => 2003-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 14971 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20040012088.pdf [firstpage_image] =>[orig_patent_app_number] => 10618721 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/618721
Semiconductor device having a ball grid array and a fabrication process thereof Jul 14, 2003 Issued
Array ( [id] => 7407494 [patent_doc_number] => 20040227234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Flash-preventing window ball grid array semiconductor package, method for fabricating the same, and chip carrier used in the semiconductor package' [patent_app_type] => new [patent_app_number] => 10/618011 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20040227234.pdf [firstpage_image] =>[orig_patent_app_number] => 10618011 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/618011
Flash-preventing window ball grid array semiconductor package, method for fabricating the same, and chip carrier used in the semiconductor package Jul 10, 2003 Issued
Array ( [id] => 1136803 [patent_doc_number] => 06784558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Semiconductor device inlcluding optimized driver layout for integrated circuit with staggered bond pads' [patent_app_type] => B2 [patent_app_number] => 10/618381 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1983 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784558.pdf [firstpage_image] =>[orig_patent_app_number] => 10618381 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/618381
Semiconductor device inlcluding optimized driver layout for integrated circuit with staggered bond pads Jul 10, 2003 Issued
Array ( [id] => 7388555 [patent_doc_number] => 20040017012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device' [patent_app_type] => new [patent_app_number] => 10/616981 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 71 [patent_figures_cnt] => 71 [patent_no_of_words] => 31440 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20040017012.pdf [firstpage_image] =>[orig_patent_app_number] => 10616981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/616981
Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device Jul 10, 2003 Issued
Array ( [id] => 7086627 [patent_doc_number] => 20050006739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Semiconductor packages for enhanced number of terminals, speed and power performance' [patent_app_type] => utility [patent_app_number] => 10/614851 [patent_app_country] => US [patent_app_date] => 2003-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5470 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20050006739.pdf [firstpage_image] =>[orig_patent_app_number] => 10614851 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/614851
Semiconductor packages for enhanced number of terminals, speed and power performance Jul 7, 2003 Issued
Menu