Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7427722 [patent_doc_number] => 20040007775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-15 [patent_title] => 'Semiconductor package and fabrication method of the same' [patent_app_type] => new [patent_app_number] => 10/614671 [patent_app_country] => US [patent_app_date] => 2003-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2443 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20040007775.pdf [firstpage_image] =>[orig_patent_app_number] => 10614671 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/614671
Semiconductor package and fabrication method of the same Jul 6, 2003 Issued
Array ( [id] => 1081420 [patent_doc_number] => 06836026 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-28 [patent_title] => 'Integrated circuit design for both input output limited and core limited integrated circuits' [patent_app_type] => B1 [patent_app_number] => 10/614402 [patent_app_country] => US [patent_app_date] => 2003-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/836/06836026.pdf [firstpage_image] =>[orig_patent_app_number] => 10614402 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/614402
Integrated circuit design for both input output limited and core limited integrated circuits Jul 2, 2003 Issued
Array ( [id] => 1102777 [patent_doc_number] => 06815813 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-09 [patent_title] => 'Self-contained heat sink and a method for fabricating same' [patent_app_type] => B1 [patent_app_number] => 10/604211 [patent_app_country] => US [patent_app_date] => 2003-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4404 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815813.pdf [firstpage_image] =>[orig_patent_app_number] => 10604211 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604211
Self-contained heat sink and a method for fabricating same Jun 30, 2003 Issued
Array ( [id] => 1136678 [patent_doc_number] => 06784539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Thermally enhanced semiconductor chip having integrated bonds over active circuits' [patent_app_type] => B2 [patent_app_number] => 10/603711 [patent_app_country] => US [patent_app_date] => 2003-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5518 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784539.pdf [firstpage_image] =>[orig_patent_app_number] => 10603711 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/603711
Thermally enhanced semiconductor chip having integrated bonds over active circuits Jun 24, 2003 Issued
Array ( [id] => 1006061 [patent_doc_number] => 06906405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Electronic part and its manufacturing method' [patent_app_type] => utility [patent_app_number] => 10/465221 [patent_app_country] => US [patent_app_date] => 2003-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 37 [patent_no_of_words] => 14261 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906405.pdf [firstpage_image] =>[orig_patent_app_number] => 10465221 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/465221
Electronic part and its manufacturing method Jun 19, 2003 Issued
Array ( [id] => 982312 [patent_doc_number] => 06927156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon' [patent_app_type] => utility [patent_app_number] => 10/465171 [patent_app_country] => US [patent_app_date] => 2003-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4875 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/927/06927156.pdf [firstpage_image] =>[orig_patent_app_number] => 10465171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/465171
Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon Jun 17, 2003 Issued
Array ( [id] => 1041000 [patent_doc_number] => 06870258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-22 [patent_title] => 'Fixture suitable for use in coupling a lid to a substrate and method' [patent_app_type] => utility [patent_app_number] => 10/458802 [patent_app_country] => US [patent_app_date] => 2003-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3349 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/870/06870258.pdf [firstpage_image] =>[orig_patent_app_number] => 10458802 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/458802
Fixture suitable for use in coupling a lid to a substrate and method Jun 15, 2003 Issued
Array ( [id] => 7323464 [patent_doc_number] => 20040251523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Stackable integrated circuit package and method therefor' [patent_app_type] => new [patent_app_number] => 10/463051 [patent_app_country] => US [patent_app_date] => 2003-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5611 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20040251523.pdf [firstpage_image] =>[orig_patent_app_number] => 10463051 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/463051
Stackable integrated circuit package and method therefor Jun 15, 2003 Issued
Array ( [id] => 961333 [patent_doc_number] => 06952046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-04 [patent_title] => 'Electronic and optoelectronic component packaging technique' [patent_app_type] => utility [patent_app_number] => 10/460852 [patent_app_country] => US [patent_app_date] => 2003-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 33 [patent_no_of_words] => 4378 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/952/06952046.pdf [firstpage_image] =>[orig_patent_app_number] => 10460852 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/460852
Electronic and optoelectronic component packaging technique Jun 12, 2003 Issued
Array ( [id] => 7250325 [patent_doc_number] => 20040238953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Built-up bump pad structure and method for same' [patent_app_type] => new [patent_app_number] => 10/449212 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2682 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20040238953.pdf [firstpage_image] =>[orig_patent_app_number] => 10449212 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/449212
Built-up bump pad structure and method for same May 29, 2003 Issued
Array ( [id] => 6699455 [patent_doc_number] => 20030222335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Circuit component, circuit component package,, circuit component built-in module, circuit component package production and circuit component built-in module production' [patent_app_type] => new [patent_app_number] => 10/448921 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 19116 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20030222335.pdf [firstpage_image] =>[orig_patent_app_number] => 10448921 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448921
Circuit component, circuit component package, circuit component built-in module, circuit component package production and circuit component built-in module production May 28, 2003 Issued
Array ( [id] => 1144970 [patent_doc_number] => 06777807 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Interconnect integration' [patent_app_type] => B1 [patent_app_number] => 10/448082 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2436 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777807.pdf [firstpage_image] =>[orig_patent_app_number] => 10448082 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448082
Interconnect integration May 28, 2003 Issued
Array ( [id] => 1159787 [patent_doc_number] => 06762491 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-13 [patent_title] => 'Power semiconductor device' [patent_app_type] => B1 [patent_app_number] => 10/445931 [patent_app_country] => US [patent_app_date] => 2003-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3972 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/762/06762491.pdf [firstpage_image] =>[orig_patent_app_number] => 10445931 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/445931
Power semiconductor device May 27, 2003 Issued
Array ( [id] => 1232462 [patent_doc_number] => 06693355 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Method of manufacturing a semiconductor device with an air gap formed using a photosensitive material' [patent_app_type] => B1 [patent_app_number] => 10/445561 [patent_app_country] => US [patent_app_date] => 2003-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 4177 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693355.pdf [firstpage_image] =>[orig_patent_app_number] => 10445561 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/445561
Method of manufacturing a semiconductor device with an air gap formed using a photosensitive material May 26, 2003 Issued
Array ( [id] => 6699462 [patent_doc_number] => 20030222342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Multi-chip package' [patent_app_type] => new [patent_app_number] => 10/442281 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3394 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20030222342.pdf [firstpage_image] =>[orig_patent_app_number] => 10442281 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/442281
Multi-chip package May 20, 2003 Issued
Array ( [id] => 1172183 [patent_doc_number] => 06753607 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Structure for improving interlevel conductor connections' [patent_app_type] => B1 [patent_app_number] => 10/441511 [patent_app_country] => US [patent_app_date] => 2003-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 849 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/753/06753607.pdf [firstpage_image] =>[orig_patent_app_number] => 10441511 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/441511
Structure for improving interlevel conductor connections May 18, 2003 Issued
Array ( [id] => 1229999 [patent_doc_number] => 06696753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-24 [patent_title] => 'Enhancement of wire bondability in semiconductor device package' [patent_app_type] => B2 [patent_app_number] => 10/438981 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5499 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/696/06696753.pdf [firstpage_image] =>[orig_patent_app_number] => 10438981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/438981
Enhancement of wire bondability in semiconductor device package May 15, 2003 Issued
Array ( [id] => 1113786 [patent_doc_number] => 06803649 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-12 [patent_title] => 'Electronic assembly' [patent_app_type] => B1 [patent_app_number] => 10/440322 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/803/06803649.pdf [firstpage_image] =>[orig_patent_app_number] => 10440322 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/440322
Electronic assembly May 15, 2003 Issued
Array ( [id] => 1102829 [patent_doc_number] => 06815835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Single sided adhesive tape for compound diversion on BOC substrates' [patent_app_type] => B2 [patent_app_number] => 10/438921 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1554 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815835.pdf [firstpage_image] =>[orig_patent_app_number] => 10438921 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/438921
Single sided adhesive tape for compound diversion on BOC substrates May 15, 2003 Issued
Array ( [id] => 1150474 [patent_doc_number] => 06774499 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-10 [patent_title] => 'Non-leaded semiconductor package and method of fabricating the same' [patent_app_type] => B1 [patent_app_number] => 10/437562 [patent_app_country] => US [patent_app_date] => 2003-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2181 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774499.pdf [firstpage_image] =>[orig_patent_app_number] => 10437562 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/437562
Non-leaded semiconductor package and method of fabricating the same May 12, 2003 Issued
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