Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1172120 [patent_doc_number] => 06753596 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Resin-sealed semiconductor device' [patent_app_type] => B1 [patent_app_number] => 10/436262 [patent_app_country] => US [patent_app_date] => 2003-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3709 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/753/06753596.pdf [firstpage_image] =>[orig_patent_app_number] => 10436262 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436262
Resin-sealed semiconductor device May 12, 2003 Issued
Array ( [id] => 1116878 [patent_doc_number] => 06800886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => B2 [patent_app_number] => 10/435471 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 7131 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/800/06800886.pdf [firstpage_image] =>[orig_patent_app_number] => 10435471 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435471
Semiconductor device and method for fabricating the same May 11, 2003 Issued
Array ( [id] => 1128443 [patent_doc_number] => 06791190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-14 [patent_title] => 'Self-aligned contact/borderless contact opening and method for forming same' [patent_app_type] => B1 [patent_app_number] => 10/434751 [patent_app_country] => US [patent_app_date] => 2003-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2461 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/791/06791190.pdf [firstpage_image] =>[orig_patent_app_number] => 10434751 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/434751
Self-aligned contact/borderless contact opening and method for forming same May 8, 2003 Issued
Array ( [id] => 7629376 [patent_doc_number] => 06818980 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Stacked semiconductor package and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 10/430331 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 2338 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818980.pdf [firstpage_image] =>[orig_patent_app_number] => 10430331 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/430331
Stacked semiconductor package and method of manufacturing the same May 6, 2003 Issued
Array ( [id] => 1063792 [patent_doc_number] => 06849956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Semiconductor integrated circuit with shortened pad pitch' [patent_app_type] => utility [patent_app_number] => 10/430341 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2738 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/849/06849956.pdf [firstpage_image] =>[orig_patent_app_number] => 10430341 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/430341
Semiconductor integrated circuit with shortened pad pitch May 6, 2003 Issued
Array ( [id] => 6809213 [patent_doc_number] => 20030199152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Method of forming a conductive contact' [patent_app_type] => new [patent_app_number] => 10/431061 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6485 [patent_no_of_claims] => 100 [patent_no_of_ind_claims] => 25 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20030199152.pdf [firstpage_image] =>[orig_patent_app_number] => 10431061 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/431061
Method of forming a conductive contact May 6, 2003 Issued
Array ( [id] => 7291807 [patent_doc_number] => 20040212054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'System and method of reducing die attach stress and strain' [patent_app_type] => new [patent_app_number] => 10/423571 [patent_app_country] => US [patent_app_date] => 2003-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5001 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20040212054.pdf [firstpage_image] =>[orig_patent_app_number] => 10423571 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/423571
System and method of reducing die attach stress and strain Apr 23, 2003 Issued
Array ( [id] => 994012 [patent_doc_number] => 06917113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-12 [patent_title] => 'Lead-free alloys for column/ball grid arrays, organic interposers and passive component assembly' [patent_app_type] => utility [patent_app_number] => 10/249621 [patent_app_country] => US [patent_app_date] => 2003-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4863 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/917/06917113.pdf [firstpage_image] =>[orig_patent_app_number] => 10249621 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/249621
Lead-free alloys for column/ball grid arrays, organic interposers and passive component assembly Apr 23, 2003 Issued
Array ( [id] => 944358 [patent_doc_number] => 06967412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Wafer level underfill and interconnect process' [patent_app_type] => utility [patent_app_number] => 10/421971 [patent_app_country] => US [patent_app_date] => 2003-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2302 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967412.pdf [firstpage_image] =>[orig_patent_app_number] => 10421971 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/421971
Wafer level underfill and interconnect process Apr 21, 2003 Issued
Array ( [id] => 1180469 [patent_doc_number] => 06744131 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Flip chip integrated circuit packages accommodating exposed chip capacitors while providing structural rigidity' [patent_app_type] => B1 [patent_app_number] => 10/421486 [patent_app_country] => US [patent_app_date] => 2003-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3244 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744131.pdf [firstpage_image] =>[orig_patent_app_number] => 10421486 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/421486
Flip chip integrated circuit packages accommodating exposed chip capacitors while providing structural rigidity Apr 21, 2003 Issued
Array ( [id] => 1074111 [patent_doc_number] => 06838776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Circuit device with at least partial packaging and method for forming' [patent_app_type] => utility [patent_app_number] => 10/418763 [patent_app_country] => US [patent_app_date] => 2003-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4170 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838776.pdf [firstpage_image] =>[orig_patent_app_number] => 10418763 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/418763
Circuit device with at least partial packaging and method for forming Apr 17, 2003 Issued
Array ( [id] => 7386856 [patent_doc_number] => 20040021231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Semiconductor device and its manufacturing method' [patent_app_type] => new [patent_app_number] => 10/417092 [patent_app_country] => US [patent_app_date] => 2003-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9449 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20040021231.pdf [firstpage_image] =>[orig_patent_app_number] => 10417092 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/417092
Semiconductor device and its manufacturing method Apr 16, 2003 Issued
Array ( [id] => 7067042 [patent_doc_number] => 20050242424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'Semiconductor device using semiconductor chip' [patent_app_type] => utility [patent_app_number] => 10/521301 [patent_app_country] => US [patent_app_date] => 2003-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7891 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20050242424.pdf [firstpage_image] =>[orig_patent_app_number] => 10521301 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/521301
Semiconductor device using semiconductor chip Apr 15, 2003 Issued
Array ( [id] => 1241547 [patent_doc_number] => 06683370 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'Semiconductor component and method of manufacturing same' [patent_app_type] => B1 [patent_app_number] => 10/417992 [patent_app_country] => US [patent_app_date] => 2003-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3868 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/683/06683370.pdf [firstpage_image] =>[orig_patent_app_number] => 10417992 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/417992
Semiconductor component and method of manufacturing same Apr 14, 2003 Issued
Array ( [id] => 7411395 [patent_doc_number] => 20040206988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'SUBSTRATE WITH EMBEDDED FREE SPACE OPTICAL INTERCONNECTS' [patent_app_type] => new [patent_app_number] => 10/414932 [patent_app_country] => US [patent_app_date] => 2003-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6233 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20040206988.pdf [firstpage_image] =>[orig_patent_app_number] => 10414932 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/414932
Substrate with embedded free space optical interconnects Apr 14, 2003 Issued
Array ( [id] => 6807339 [patent_doc_number] => 20030197278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Structure of integrated trace of chip package' [patent_app_type] => new [patent_app_number] => 10/413796 [patent_app_country] => US [patent_app_date] => 2003-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3433 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20030197278.pdf [firstpage_image] =>[orig_patent_app_number] => 10413796 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/413796
Structure of integrated trace of chip package Apr 13, 2003 Issued
Array ( [id] => 1125196 [patent_doc_number] => 06794693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => B2 [patent_app_number] => 10/408581 [patent_app_country] => US [patent_app_date] => 2003-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5511 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/794/06794693.pdf [firstpage_image] =>[orig_patent_app_number] => 10408581 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/408581
Semiconductor device and manufacturing method thereof Apr 7, 2003 Issued
Array ( [id] => 6863710 [patent_doc_number] => 20030189236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'Surface-mountable light-emitting diode structural element' [patent_app_type] => new [patent_app_number] => 10/407734 [patent_app_country] => US [patent_app_date] => 2003-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4048 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20030189236.pdf [firstpage_image] =>[orig_patent_app_number] => 10407734 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/407734
Optoelectric surface-mountable structural element Apr 3, 2003 Issued
Array ( [id] => 7388491 [patent_doc_number] => 20040017000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Integrated circuit package with exposed die surfaces and auxiliary attachment' [patent_app_type] => new [patent_app_number] => 10/400207 [patent_app_country] => US [patent_app_date] => 2003-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5010 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20040017000.pdf [firstpage_image] =>[orig_patent_app_number] => 10400207 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/400207
Integrated circuit package with exposed die surfaces and auxiliary attachment Mar 26, 2003 Issued
Array ( [id] => 6727758 [patent_doc_number] => 20030183948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Golden unit' [patent_app_type] => new [patent_app_number] => 10/402555 [patent_app_country] => US [patent_app_date] => 2003-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2096 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0183/20030183948.pdf [firstpage_image] =>[orig_patent_app_number] => 10402555 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/402555
Golden unit Mar 26, 2003 Abandoned
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