Jasmine Jhihan B. Clark

Array ( [id] => 7393892 [patent_doc_number] => 20040173911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/482012 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2912 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20040173911.pdf [firstpage_image] =>[orig_patent_app_number] => 10482012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 968877 [patent_doc_number] => 06940154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'Integrated circuit package and method of manufacturing the integrated circuit package' [patent_app_type] => utility [patent_app_number] => 10/178372 [patent_app_country] => US [patent_app_date] => 2002-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 3725 [patent_no_of_claims] => 99 [patent_no_of_ind_claims] => 32 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/940/06940154.pdf [firstpage_image] =>[orig_patent_app_number] => 10178372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1241536 [patent_doc_number] => 06683359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-27 [patent_title] => 'Hall effect device with multiple layers' [patent_app_type] => B2 [patent_app_number] => 10/176002 [patent_app_country] => US [patent_app_date] => 2002-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6288 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/683/06683359.pdf [firstpage_image] =>[orig_patent_app_number] => 10176002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1277080 [patent_doc_number] => 06650014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-18 [patent_title] => 'Semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/170842 [patent_app_country] => US [patent_app_date] => 2002-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 6885 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/650/06650014.pdf [firstpage_image] =>[orig_patent_app_number] => 10170842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6254666 [patent_doc_number] => 20020185736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Semiconductor device with elongated interconnecting member and fabrication method thereof' [patent_app_type] => new [patent_app_number] => 10/166182 [patent_app_country] => US [patent_app_date] => 2002-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12678 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20020185736.pdf [firstpage_image] =>[orig_patent_app_number] => 10166182 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1369091 [patent_doc_number] => 06570263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Structure of plated wire of fiducial marks for die-dicing package' [patent_app_type] => B1 [patent_app_number] => 10/162912 [patent_app_country] => US [patent_app_date] => 2002-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1557 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/570/06570263.pdf [firstpage_image] =>[orig_patent_app_number] => 10162912 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1225072 [patent_doc_number] => 06700143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Dummy structures that protect circuit elements during polishing' [patent_app_type] => B2 [patent_app_number] => 10/165741 [patent_app_country] => US [patent_app_date] => 2002-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3364 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/700/06700143.pdf [firstpage_image] =>[orig_patent_app_number] => 10165741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6666744 [patent_doc_number] => 20030111727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Semiconductor integrated circuit device and printed wired board for mounting the same' [patent_app_type] => new [patent_app_number] => 10/157981 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6640 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20030111727.pdf [firstpage_image] =>[orig_patent_app_number] => 10157981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1277032 [patent_doc_number] => 06650005 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-18 [patent_title] => 'Micro BGA package' [patent_app_type] => B2 [patent_app_number] => 10/156002 [patent_app_country] => US [patent_app_date] => 2002-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1834 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/650/06650005.pdf [firstpage_image] =>[orig_patent_app_number] => 10156002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6385056 [patent_doc_number] => 20020179967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/156641 [patent_app_country] => US [patent_app_date] => 2002-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 9821 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20020179967.pdf [firstpage_image] =>[orig_patent_app_number] => 10156641 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1306026 [patent_doc_number] => 06621130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'Semiconductor device and an electronic device' [patent_app_type] => B2 [patent_app_number] => 10/156512 [patent_app_country] => US [patent_app_date] => 2002-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 37 [patent_no_of_words] => 12870 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/621/06621130.pdf [firstpage_image] =>[orig_patent_app_number] => 10156512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1420457 [patent_doc_number] => 06521923 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Microwave field effect transistor structure on silicon carbide substrate' [patent_app_type] => B1 [patent_app_number] => 10/156221 [patent_app_country] => US [patent_app_date] => 2002-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 9510 [patent_no_of_claims] => 76 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/521/06521923.pdf [firstpage_image] =>[orig_patent_app_number] => 10156221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1306018 [patent_doc_number] => 06621129 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'MROM memory cell structure for storing multi level bit information' [patent_app_type] => B1 [patent_app_number] => 10/153892 [patent_app_country] => US [patent_app_date] => 2002-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2271 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/621/06621129.pdf [firstpage_image] =>[orig_patent_app_number] => 10153892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7623503 [patent_doc_number] => 06686662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-03 [patent_title] => 'Semiconductor device barrier layer' [patent_app_type] => B2 [patent_app_number] => 10/153231 [patent_app_country] => US [patent_app_date] => 2002-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3012 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/686/06686662.pdf [firstpage_image] =>[orig_patent_app_number] => 10153231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6427648 [patent_doc_number] => 20020175403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Thermal interface material and heat sink configuration' [patent_app_type] => new [patent_app_number] => 10/151741 [patent_app_country] => US [patent_app_date] => 2002-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4695 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20020175403.pdf [firstpage_image] =>[orig_patent_app_number] => 10151741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1300333 [patent_doc_number] => 06628001 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Integrated circuit die having alignment marks in the bond pad region and method of manufacturing same' [patent_app_type] => B1 [patent_app_number] => 10/150790 [patent_app_country] => US [patent_app_date] => 2002-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2658 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/628/06628001.pdf [firstpage_image] =>[orig_patent_app_number] => 10150790 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6845374 [patent_doc_number] => 20030164541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-04 [patent_title] => 'Method and apparatus for dielectric filling of flip chip on interposer assembly' [patent_app_type] => new [patent_app_number] => 10/150902 [patent_app_country] => US [patent_app_date] => 2002-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12957 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20030164541.pdf [firstpage_image] =>[orig_patent_app_number] => 10150902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1266565 [patent_doc_number] => 06661090 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Metal adhesion layer in an integrated circuit package' [patent_app_type] => B1 [patent_app_number] => 10/150232 [patent_app_country] => US [patent_app_date] => 2002-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2164 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/661/06661090.pdf [firstpage_image] =>[orig_patent_app_number] => 10150232 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1310190 [patent_doc_number] => 06617678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-09 [patent_title] => 'Semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/145722 [patent_app_country] => US [patent_app_date] => 2002-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 11085 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/617/06617678.pdf [firstpage_image] =>[orig_patent_app_number] => 10145722 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6768058 [patent_doc_number] => 20030213998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Variable resistor structure and method for forming and programming a variable resistor for electronic circuits' [patent_app_type] => new [patent_app_number] => 10/146072 [patent_app_country] => US [patent_app_date] => 2002-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6146 [patent_no_of_claims] => 72 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20030213998.pdf [firstpage_image] =>[orig_patent_app_number] => 10146072 [rel_patent_id] =>[rel_patent_doc_number] =>)