Jasmine Jhihan B. Clark

Array ( [id] => 6012308 [patent_doc_number] => 20020100931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Method and composite for decreasing charge leakage' [patent_app_type] => new [patent_app_number] => 10/060532 [patent_app_country] => US [patent_app_date] => 2002-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3702 [patent_no_of_claims] => 234 [patent_no_of_ind_claims] => 50 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20020100931.pdf [firstpage_image] =>[orig_patent_app_number] => 10060532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5981952 [patent_doc_number] => 20020096715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/057642 [patent_app_country] => US [patent_app_date] => 2002-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8458 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20020096715.pdf [firstpage_image] =>[orig_patent_app_number] => 10057642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6349074 [patent_doc_number] => 20020056904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/051009 [patent_app_country] => US [patent_app_date] => 2002-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8713 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20020056904.pdf [firstpage_image] =>[orig_patent_app_number] => 10051009 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6349082 [patent_doc_number] => 20020056905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/051077 [patent_app_country] => US [patent_app_date] => 2002-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8714 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20020056905.pdf [firstpage_image] =>[orig_patent_app_number] => 10051077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1407353 [patent_doc_number] => 06538327 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Method of copper interconnect formation using atomic layer copper deposition and a device thereby formed' [patent_app_type] => B1 [patent_app_number] => 10/052831 [patent_app_country] => US [patent_app_date] => 2002-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4173 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538327.pdf [firstpage_image] =>[orig_patent_app_number] => 10052831 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1025598 [patent_doc_number] => 06885106 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-26 [patent_title] => 'Stacked microelectronic assemblies and methods of making same' [patent_app_type] => utility [patent_app_number] => 10/044121 [patent_app_country] => US [patent_app_date] => 2002-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8536 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/885/06885106.pdf [firstpage_image] =>[orig_patent_app_number] => 10044121 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1180461 [patent_doc_number] => 06744129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'Integrated ground shield' [patent_app_type] => B2 [patent_app_number] => 10/043911 [patent_app_country] => US [patent_app_date] => 2002-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1440 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/744/06744129.pdf [firstpage_image] =>[orig_patent_app_number] => 10043911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1441078 [patent_doc_number] => 06495925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Semiconductor chip and a lead frame' [patent_app_type] => B1 [patent_app_number] => 09/856192 [patent_app_country] => US [patent_app_date] => 2002-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1730 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495925.pdf [firstpage_image] =>[orig_patent_app_number] => 09856192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1424273 [patent_doc_number] => 06515335 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same' [patent_app_type] => B1 [patent_app_number] => 10/037611 [patent_app_country] => US [patent_app_date] => 2002-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5654 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515335.pdf [firstpage_image] =>[orig_patent_app_number] => 10037611 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1120914 [patent_doc_number] => 06798053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'IC chip package' [patent_app_type] => B2 [patent_app_number] => 10/033932 [patent_app_country] => US [patent_app_date] => 2002-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2195 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/798/06798053.pdf [firstpage_image] =>[orig_patent_app_number] => 10033932 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1536573 [patent_doc_number] => 06489685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-03 [patent_title] => 'Component built-in module and method of manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 10/038212 [patent_app_country] => US [patent_app_date] => 2002-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 32 [patent_no_of_words] => 12175 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/489/06489685.pdf [firstpage_image] =>[orig_patent_app_number] => 10038212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1421623 [patent_doc_number] => 06509636 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Semiconductor package' [patent_app_type] => B1 [patent_app_number] => 10/039251 [patent_app_country] => US [patent_app_date] => 2002-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2140 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509636.pdf [firstpage_image] =>[orig_patent_app_number] => 10039251 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1406952 [patent_doc_number] => 06538306 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Electronic part' [patent_app_type] => B1 [patent_app_number] => 10/019391 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 49 [patent_no_of_words] => 4542 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/538/06538306.pdf [firstpage_image] =>[orig_patent_app_number] => 10019391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1455593 [patent_doc_number] => 06462427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-08 [patent_title] => 'Semiconductor chip, set of semiconductor chips and multichip module' [patent_app_type] => B2 [patent_app_number] => 10/024721 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6310 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/462/06462427.pdf [firstpage_image] =>[orig_patent_app_number] => 10024721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5825918 [patent_doc_number] => 20020066934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Eeprom with high channel hot carrier injection efficiency' [patent_app_type] => new [patent_app_number] => 10/022337 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 11030 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20020066934.pdf [firstpage_image] =>[orig_patent_app_number] => 10022337 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1375010 [patent_doc_number] => 06566746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-20 [patent_title] => 'Panel stacking of BGA devices to form three-dimensional modules' [patent_app_type] => B2 [patent_app_number] => 10/017553 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 9963 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566746.pdf [firstpage_image] =>[orig_patent_app_number] => 10017553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5918086 [patent_doc_number] => 20020113306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Semiconductor packages' [patent_app_type] => new [patent_app_number] => 10/017801 [patent_app_country] => US [patent_app_date] => 2001-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2210 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20020113306.pdf [firstpage_image] =>[orig_patent_app_number] => 10017801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6764102 [patent_doc_number] => 20030098500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => '180 DEGREE BUMP PLACEMENT LAYOUT FOR AN INTEGRATED CIRCUIT POWER GRID' [patent_app_type] => new [patent_app_number] => 09/997452 [patent_app_country] => US [patent_app_date] => 2001-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4761 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20030098500.pdf [firstpage_image] =>[orig_patent_app_number] => 09997452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1421116 [patent_doc_number] => 06521985 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Method for the production of a portable integrated circuit electronic device comprising a low-cost dielectric' [patent_app_type] => B1 [patent_app_number] => 09/979601 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4239 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/521/06521985.pdf [firstpage_image] =>[orig_patent_app_number] => 09979601 [rel_patent_id] =>[rel_patent_doc_number] =>)