Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1522304 [patent_doc_number] => 06414380 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Semiconductor device and method of making same' [patent_app_type] => B1 [patent_app_number] => 09/956801 [patent_app_country] => US [patent_app_date] => 2001-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 20 [patent_no_of_words] => 2659 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414380.pdf [firstpage_image] =>[orig_patent_app_number] => 09956801 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/956801
Semiconductor device and method of making same Sep 20, 2001 Issued
Array ( [id] => 6713807 [patent_doc_number] => 20030025155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'High-voltage transistor with multi-layer conduction region' [patent_app_type] => new [patent_app_number] => 09/961221 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7593 [patent_no_of_claims] => 102 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20030025155.pdf [firstpage_image] =>[orig_patent_app_number] => 09961221 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/961221
High-voltage transistor with multi-layer conduction region Sep 19, 2001 Issued
Array ( [id] => 7639786 [patent_doc_number] => 06396130 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Semiconductor package having multiple dies with independently biased back surfaces' [patent_app_type] => B1 [patent_app_number] => 09/953422 [patent_app_country] => US [patent_app_date] => 2001-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4991 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396130.pdf [firstpage_image] =>[orig_patent_app_number] => 09953422 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/953422
Semiconductor package having multiple dies with independently biased back surfaces Sep 13, 2001 Issued
Array ( [id] => 1476448 [patent_doc_number] => 06388340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-14 [patent_title] => 'Compliant semiconductor chip package with fan-out leads and method of making same' [patent_app_type] => B2 [patent_app_number] => 09/950132 [patent_app_country] => US [patent_app_date] => 2001-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 9331 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388340.pdf [firstpage_image] =>[orig_patent_app_number] => 09950132 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/950132
Compliant semiconductor chip package with fan-out leads and method of making same Sep 9, 2001 Issued
Array ( [id] => 6060392 [patent_doc_number] => 20020030267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Compound semiconductor device' [patent_app_type] => new [patent_app_number] => 09/945622 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8698 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20020030267.pdf [firstpage_image] =>[orig_patent_app_number] => 09945622 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/945622
Compound semiconductor device Sep 4, 2001 Issued
Array ( [id] => 6502024 [patent_doc_number] => 20020025602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Microelectronic assembly with pre-disposed fill material and associated method of manufacture' [patent_app_type] => new [patent_app_number] => 09/946291 [patent_app_country] => US [patent_app_date] => 2001-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3845 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20020025602.pdf [firstpage_image] =>[orig_patent_app_number] => 09946291 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/946291
Microelectronic assembly with pre-disposed fill material and associated method of manufacture Sep 3, 2001 Issued
Array ( [id] => 7623511 [patent_doc_number] => 06686654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-03 [patent_title] => 'Multiple chip stack structure and cooling system' [patent_app_type] => B2 [patent_app_number] => 09/945042 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6591 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/686/06686654.pdf [firstpage_image] =>[orig_patent_app_number] => 09945042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/945042
Multiple chip stack structure and cooling system Aug 30, 2001 Issued
Array ( [id] => 1178686 [patent_doc_number] => 06747347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-08 [patent_title] => 'Multi-chip electronic package and cooling system' [patent_app_type] => B2 [patent_app_number] => 09/945024 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5589 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/747/06747347.pdf [firstpage_image] =>[orig_patent_app_number] => 09945024 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/945024
Multi-chip electronic package and cooling system Aug 29, 2001 Issued
Array ( [id] => 1404703 [patent_doc_number] => 06531776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-11 [patent_title] => 'Semiconductor device having reduced interconnect-line parasitic capacitance' [patent_app_type] => B2 [patent_app_number] => 09/940852 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2428 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531776.pdf [firstpage_image] =>[orig_patent_app_number] => 09940852 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/940852
Semiconductor device having reduced interconnect-line parasitic capacitance Aug 28, 2001 Issued
Array ( [id] => 1404491 [patent_doc_number] => 06531764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-11 [patent_title] => 'Vertically mountable semiconductor device, assembly, and methods' [patent_app_type] => B2 [patent_app_number] => 09/939849 [patent_app_country] => US [patent_app_date] => 2001-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 4803 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531764.pdf [firstpage_image] =>[orig_patent_app_number] => 09939849 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939849
Vertically mountable semiconductor device, assembly, and methods Aug 26, 2001 Issued
Array ( [id] => 7433374 [patent_doc_number] => 20040065881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Ceramic substrate for semiconductor production and inspection' [patent_app_type] => new [patent_app_number] => 10/362941 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12014 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20040065881.pdf [firstpage_image] =>[orig_patent_app_number] => 10362941 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/362941
Ceramic substrate for semiconductor production and inspection Aug 23, 2001 Issued
Array ( [id] => 5997198 [patent_doc_number] => 20020027277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Deflectable interconnect' [patent_app_type] => new [patent_app_number] => 09/929455 [patent_app_country] => US [patent_app_date] => 2001-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6750 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20020027277.pdf [firstpage_image] =>[orig_patent_app_number] => 09929455 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/929455
Deflectable interconnect Aug 13, 2001 Issued
Array ( [id] => 1314606 [patent_doc_number] => 06614123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-02 [patent_title] => 'Plastic ball grid array package with integral heatsink' [patent_app_type] => B2 [patent_app_number] => 09/919763 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3533 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/614/06614123.pdf [firstpage_image] =>[orig_patent_app_number] => 09919763 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/919763
Plastic ball grid array package with integral heatsink Jul 30, 2001 Issued
Array ( [id] => 1404067 [patent_doc_number] => 06541850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'Utilization of die active surfaces for laterally extending die internal and external connections' [patent_app_type] => B2 [patent_app_number] => 09/917130 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3980 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/541/06541850.pdf [firstpage_image] =>[orig_patent_app_number] => 09917130 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/917130
Utilization of die active surfaces for laterally extending die internal and external connections Jul 26, 2001 Issued
Array ( [id] => 1420894 [patent_doc_number] => 06512303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-28 [patent_title] => 'Flip chip adaptor package for bare die' [patent_app_type] => B2 [patent_app_number] => 09/911160 [patent_app_country] => US [patent_app_date] => 2001-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2896 [patent_no_of_claims] => 114 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/512/06512303.pdf [firstpage_image] =>[orig_patent_app_number] => 09911160 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/911160
Flip chip adaptor package for bare die Jul 22, 2001 Issued
Array ( [id] => 1424451 [patent_doc_number] => 06507094 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-14 [patent_title] => 'Die paddle clamping for wire bond enhancement' [patent_app_type] => B2 [patent_app_number] => 09/903318 [patent_app_country] => US [patent_app_date] => 2001-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3102 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507094.pdf [firstpage_image] =>[orig_patent_app_number] => 09903318 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/903318
Die paddle clamping for wire bond enhancement Jul 10, 2001 Issued
Array ( [id] => 6933370 [patent_doc_number] => 20010054714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Gate insulated field effect transistor and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/901026 [patent_app_country] => US [patent_app_date] => 2001-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8874 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20010054714.pdf [firstpage_image] =>[orig_patent_app_number] => 09901026 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/901026
Gate insulated field effect transistor and method of manufacturing the same Jul 9, 2001 Issued
Array ( [id] => 6092118 [patent_doc_number] => 20020050650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Semiconductor device and method for making the same' [patent_app_type] => new [patent_app_number] => 09/888951 [patent_app_country] => US [patent_app_date] => 2001-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3012 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20020050650.pdf [firstpage_image] =>[orig_patent_app_number] => 09888951 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/888951
Semiconductor device and method for making the same Jun 24, 2001 Issued
Array ( [id] => 1576297 [patent_doc_number] => 06469346 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'High-breakdown-voltage semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/886204 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4728 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469346.pdf [firstpage_image] =>[orig_patent_app_number] => 09886204 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/886204
High-breakdown-voltage semiconductor device Jun 21, 2001 Issued
Array ( [id] => 1536584 [patent_doc_number] => 06489687 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Semiconductor device and method of manufacturing the same, manufacturing device, circuit board, and electronic equipment' [patent_app_type] => B1 [patent_app_number] => 09/856923 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 21 [patent_no_of_words] => 11302 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/489/06489687.pdf [firstpage_image] =>[orig_patent_app_number] => 09856923 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/856923
Semiconductor device and method of manufacturing the same, manufacturing device, circuit board, and electronic equipment May 29, 2001 Issued
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