Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1509480 [patent_doc_number] => 06441477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-27 [patent_title] => 'Substrate mounting an integrated circuit package with a deformed lead' [patent_app_type] => B2 [patent_app_number] => 09/772891 [patent_app_country] => US [patent_app_date] => 2001-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3540 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/441/06441477.pdf [firstpage_image] =>[orig_patent_app_number] => 09772891 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/772891
Substrate mounting an integrated circuit package with a deformed lead Jan 30, 2001 Issued
Array ( [id] => 1480712 [patent_doc_number] => 06452279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-17 [patent_title] => 'Semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/771891 [patent_app_country] => US [patent_app_date] => 2001-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3715 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452279.pdf [firstpage_image] =>[orig_patent_app_number] => 09771891 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/771891
Semiconductor device Jan 29, 2001 Issued
Array ( [id] => 1519053 [patent_doc_number] => 06501171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Flip chip package with improved cap design and process for making thereof' [patent_app_type] => B2 [patent_app_number] => 09/774152 [patent_app_country] => US [patent_app_date] => 2001-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3538 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501171.pdf [firstpage_image] =>[orig_patent_app_number] => 09774152 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774152
Flip chip package with improved cap design and process for making thereof Jan 29, 2001 Issued
Array ( [id] => 1365009 [patent_doc_number] => 06573609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-03 [patent_title] => 'Microelectronic component with rigid interposer' [patent_app_type] => B2 [patent_app_number] => 09/771412 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 12993 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/573/06573609.pdf [firstpage_image] =>[orig_patent_app_number] => 09771412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/771412
Microelectronic component with rigid interposer Jan 25, 2001 Issued
Array ( [id] => 5982056 [patent_doc_number] => 20020096762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Structure of stacked integrated circuits and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/770082 [patent_app_country] => US [patent_app_date] => 2001-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1538 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20020096762.pdf [firstpage_image] =>[orig_patent_app_number] => 09770082 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/770082
Structure of stacked integrated circuits and method for manufacturing the same Jan 23, 2001 Abandoned
Array ( [id] => 6895230 [patent_doc_number] => 20010026020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'Shielding device and electrical structural part having a shielding device' [patent_app_type] => new [patent_app_number] => 09/768392 [patent_app_country] => US [patent_app_date] => 2001-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5835 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026020.pdf [firstpage_image] =>[orig_patent_app_number] => 09768392 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/768392
Shielding device and electrical structural part having a shielding device Jan 23, 2001 Issued
Array ( [id] => 1568447 [patent_doc_number] => 06376905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-23 [patent_title] => 'Semiconductor package' [patent_app_type] => B2 [patent_app_number] => 09/767720 [patent_app_country] => US [patent_app_date] => 2001-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3469 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376905.pdf [firstpage_image] =>[orig_patent_app_number] => 09767720 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/767720
Semiconductor package Jan 23, 2001 Issued
Array ( [id] => 5982055 [patent_doc_number] => 20020096761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'STRUCTURE OF STACKED INTEGRATED CIRCUITS AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => new [patent_app_number] => 09/770081 [patent_app_country] => US [patent_app_date] => 2001-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1618 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20020096761.pdf [firstpage_image] =>[orig_patent_app_number] => 09770081 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/770081
STRUCTURE OF STACKED INTEGRATED CIRCUITS AND METHOD FOR MANUFACTURING THE SAME Jan 23, 2001 Abandoned
Array ( [id] => 5982033 [patent_doc_number] => 20020096751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Integrated circuit structure having an adhesive agent and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/770052 [patent_app_country] => US [patent_app_date] => 2001-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1466 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20020096751.pdf [firstpage_image] =>[orig_patent_app_number] => 09770052 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/770052
Integrated circuit structure having an adhesive agent and method for manufacturing the same Jan 23, 2001 Abandoned
Array ( [id] => 1583013 [patent_doc_number] => 06424024 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Leadframe of quad flat non-leaded package' [patent_app_type] => B1 [patent_app_number] => 09/767420 [patent_app_country] => US [patent_app_date] => 2001-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3578 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424024.pdf [firstpage_image] =>[orig_patent_app_number] => 09767420 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/767420
Leadframe of quad flat non-leaded package Jan 22, 2001 Issued
Array ( [id] => 1561870 [patent_doc_number] => 06437436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-20 [patent_title] => 'Integrated circuit chip package with test points' [patent_app_type] => B2 [patent_app_number] => 09/766081 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2338 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/437/06437436.pdf [firstpage_image] =>[orig_patent_app_number] => 09766081 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/766081
Integrated circuit chip package with test points Jan 18, 2001 Issued
Array ( [id] => 5870282 [patent_doc_number] => 20020046874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Thin film metal barrier for electrical interconnections' [patent_app_type] => new [patent_app_number] => 09/759258 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3301 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20020046874.pdf [firstpage_image] =>[orig_patent_app_number] => 09759258 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/759258
Thin film metal barrier for electrical interconnections Jan 15, 2001 Issued
Array ( [id] => 6300699 [patent_doc_number] => 20020093108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Flip chip packaged semiconductor device having double stud bumps and method of forming same' [patent_app_type] => new [patent_app_number] => 09/760951 [patent_app_country] => US [patent_app_date] => 2001-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3217 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20020093108.pdf [firstpage_image] =>[orig_patent_app_number] => 09760951 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/760951
Flip chip packaged semiconductor device having double stud bumps and method of forming same Jan 14, 2001 Abandoned
Array ( [id] => 1596990 [patent_doc_number] => 06384426 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'System for testing semiconductor chip leads constrained in dielectric media' [patent_app_type] => B1 [patent_app_number] => 09/756958 [patent_app_country] => US [patent_app_date] => 2001-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 1 [patent_no_of_words] => 5898 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/384/06384426.pdf [firstpage_image] =>[orig_patent_app_number] => 09756958 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/756958
System for testing semiconductor chip leads constrained in dielectric media Jan 8, 2001 Issued
Array ( [id] => 1603229 [patent_doc_number] => 06433409 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Semiconductor device, lead-patterning substrate, and electronics device, and method for fabricating same' [patent_app_type] => B1 [patent_app_number] => 09/755179 [patent_app_country] => US [patent_app_date] => 2001-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 56 [patent_no_of_words] => 16988 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/433/06433409.pdf [firstpage_image] =>[orig_patent_app_number] => 09755179 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755179
Semiconductor device, lead-patterning substrate, and electronics device, and method for fabricating same Jan 7, 2001 Issued
Array ( [id] => 1597161 [patent_doc_number] => 06384471 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Pbga package with integrated ball grid' [patent_app_type] => B1 [patent_app_number] => 09/743061 [patent_app_country] => US [patent_app_date] => 2001-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/384/06384471.pdf [firstpage_image] =>[orig_patent_app_number] => 09743061 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/743061
Pbga package with integrated ball grid Jan 3, 2001 Issued
Array ( [id] => 7639759 [patent_doc_number] => 06396157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-28 [patent_title] => 'Semiconductor integrated circuit device and manufacturing method thereof' [patent_app_type] => B2 [patent_app_number] => 09/752682 [patent_app_country] => US [patent_app_date] => 2001-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 6504 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396157.pdf [firstpage_image] =>[orig_patent_app_number] => 09752682 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752682
Semiconductor integrated circuit device and manufacturing method thereof Jan 2, 2001 Issued
Array ( [id] => 1422871 [patent_doc_number] => 06518678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-11 [patent_title] => 'Apparatus and method for reducing interposer compression during molding process' [patent_app_type] => B2 [patent_app_number] => 09/749872 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2337 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518678.pdf [firstpage_image] =>[orig_patent_app_number] => 09749872 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/749872
Apparatus and method for reducing interposer compression during molding process Dec 28, 2000 Issued
Array ( [id] => 1471659 [patent_doc_number] => 06407446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-18 [patent_title] => 'Leadframe and semiconductor chip package having cutout portions and increased lead count' [patent_app_type] => B2 [patent_app_number] => 09/751710 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 2227 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407446.pdf [firstpage_image] =>[orig_patent_app_number] => 09751710 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/751710
Leadframe and semiconductor chip package having cutout portions and increased lead count Dec 27, 2000 Issued
Array ( [id] => 1497057 [patent_doc_number] => 06404026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-11 [patent_title] => 'Semiconductor devices' [patent_app_type] => B2 [patent_app_number] => 09/749020 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7593 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404026.pdf [firstpage_image] =>[orig_patent_app_number] => 09749020 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/749020
Semiconductor devices Dec 26, 2000 Issued
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