Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1597178 [patent_doc_number] => 06384475 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Lead formation using grids' [patent_app_type] => B1 [patent_app_number] => 09/535620 [patent_app_country] => US [patent_app_date] => 2000-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4636 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/384/06384475.pdf [firstpage_image] =>[orig_patent_app_number] => 09535620 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/535620
Lead formation using grids Mar 26, 2000 Issued
Array ( [id] => 7643520 [patent_doc_number] => 06429521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Semiconductor integrated circuit device and its manufacturing method' [patent_app_type] => B1 [patent_app_number] => 09/531177 [patent_app_country] => US [patent_app_date] => 2000-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 6480 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429521.pdf [firstpage_image] =>[orig_patent_app_number] => 09531177 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531177
Semiconductor integrated circuit device and its manufacturing method Mar 20, 2000 Issued
Array ( [id] => 1522316 [patent_doc_number] => 06414386 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Method to reduce number of wire-bond loop heights versus the total quantity of power and signal rings' [patent_app_type] => B1 [patent_app_number] => 09/531971 [patent_app_country] => US [patent_app_date] => 2000-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2601 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414386.pdf [firstpage_image] =>[orig_patent_app_number] => 09531971 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531971
Method to reduce number of wire-bond loop heights versus the total quantity of power and signal rings Mar 19, 2000 Issued
Array ( [id] => 4278189 [patent_doc_number] => 06323545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/508812 [patent_app_country] => US [patent_app_date] => 2000-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2475 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323545.pdf [firstpage_image] =>[orig_patent_app_number] => 508812 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/508812
Semiconductor device Mar 16, 2000 Issued
Array ( [id] => 1516246 [patent_doc_number] => 06420790 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/522923 [patent_app_country] => US [patent_app_date] => 2000-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1847 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420790.pdf [firstpage_image] =>[orig_patent_app_number] => 09522923 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/522923
Semiconductor device Mar 9, 2000 Issued
Array ( [id] => 1442047 [patent_doc_number] => 06335571 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Semiconductor flip-chip package and method for the fabrication thereof' [patent_app_type] => B1 [patent_app_number] => 09/517839 [patent_app_country] => US [patent_app_date] => 2000-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 9107 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335571.pdf [firstpage_image] =>[orig_patent_app_number] => 09517839 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/517839
Semiconductor flip-chip package and method for the fabrication thereof Mar 1, 2000 Issued
Array ( [id] => 1524918 [patent_doc_number] => 06353263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => B1 [patent_app_number] => 09/517510 [patent_app_country] => US [patent_app_date] => 2000-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 9080 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353263.pdf [firstpage_image] =>[orig_patent_app_number] => 09517510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/517510
Semiconductor device and manufacturing method thereof Mar 1, 2000 Issued
Array ( [id] => 7636034 [patent_doc_number] => 06380626 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Semiconductor device for attachment to a semiconductor substrate' [patent_app_type] => B1 [patent_app_number] => 09/516047 [patent_app_country] => US [patent_app_date] => 2000-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3339 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380626.pdf [firstpage_image] =>[orig_patent_app_number] => 09516047 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/516047
Semiconductor device for attachment to a semiconductor substrate Feb 29, 2000 Issued
09/514633 Apparatus for stacking semiconductor chips Feb 27, 2000 Abandoned
Array ( [id] => 1486853 [patent_doc_number] => 06365980 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Thermally enhanced semiconductor ball grid array device and method of fabrication' [patent_app_type] => B1 [patent_app_number] => 09/513121 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 5855 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365980.pdf [firstpage_image] =>[orig_patent_app_number] => 09513121 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/513121
Thermally enhanced semiconductor ball grid array device and method of fabrication Feb 24, 2000 Issued
Array ( [id] => 1544372 [patent_doc_number] => 06373134 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Semiconductor device and fabrication method introducing horizontal side-steps into vertical steps' [patent_app_type] => B1 [patent_app_number] => 09/514030 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2784 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373134.pdf [firstpage_image] =>[orig_patent_app_number] => 09514030 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/514030
Semiconductor device and fabrication method introducing horizontal side-steps into vertical steps Feb 24, 2000 Issued
Array ( [id] => 1459957 [patent_doc_number] => 06426557 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Self-aligned last-metal C4 interconnection layer for Cu technologies' [patent_app_type] => B1 [patent_app_number] => 09/512952 [patent_app_country] => US [patent_app_date] => 2000-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2001 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426557.pdf [firstpage_image] =>[orig_patent_app_number] => 09512952 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/512952
Self-aligned last-metal C4 interconnection layer for Cu technologies Feb 24, 2000 Issued
Array ( [id] => 1497199 [patent_doc_number] => 06404061 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Semiconductor device and semiconductor chip' [patent_app_type] => B1 [patent_app_number] => 09/512061 [patent_app_country] => US [patent_app_date] => 2000-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 28 [patent_no_of_words] => 4345 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404061.pdf [firstpage_image] =>[orig_patent_app_number] => 09512061 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/512061
Semiconductor device and semiconductor chip Feb 23, 2000 Issued
Array ( [id] => 1486836 [patent_doc_number] => 06365976 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Integrated circuit device with depressions for receiving solder balls and method of fabrication' [patent_app_type] => B1 [patent_app_number] => 09/511320 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3923 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365976.pdf [firstpage_image] =>[orig_patent_app_number] => 09511320 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/511320
Integrated circuit device with depressions for receiving solder balls and method of fabrication Feb 22, 2000 Issued
Array ( [id] => 6349045 [patent_doc_number] => 20020056899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Semiconductor chip and semiconductor device having a chip-on-chip structure' [patent_app_type] => new [patent_app_number] => 09/502433 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4031 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20020056899.pdf [firstpage_image] =>[orig_patent_app_number] => 09502433 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/502433
Semiconductor chip and semiconductor device having a chip-on-chip structure Feb 10, 2000 Issued
Array ( [id] => 4361595 [patent_doc_number] => 06287482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/501242 [patent_app_country] => US [patent_app_date] => 2000-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2149 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287482.pdf [firstpage_image] =>[orig_patent_app_number] => 501242 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501242
Semiconductor device Feb 9, 2000 Issued
Array ( [id] => 7639768 [patent_doc_number] => 06396148 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Electroless metal connection structures and methods' [patent_app_type] => B1 [patent_app_number] => 09/501200 [patent_app_country] => US [patent_app_date] => 2000-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 5900 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396148.pdf [firstpage_image] =>[orig_patent_app_number] => 09501200 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501200
Electroless metal connection structures and methods Feb 9, 2000 Issued
Array ( [id] => 4414446 [patent_doc_number] => 06265778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Semiconductor device with a multi-level interconnection structure' [patent_app_type] => 1 [patent_app_number] => 9/496953 [patent_app_country] => US [patent_app_date] => 2000-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5051 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265778.pdf [firstpage_image] =>[orig_patent_app_number] => 496953 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/496953
Semiconductor device with a multi-level interconnection structure Feb 2, 2000 Issued
Array ( [id] => 1568441 [patent_doc_number] => 06376902 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Optoelectronic structural element' [patent_app_type] => B1 [patent_app_number] => 09/494771 [patent_app_country] => US [patent_app_date] => 2000-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3892 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376902.pdf [firstpage_image] =>[orig_patent_app_number] => 09494771 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/494771
Optoelectronic structural element Jan 30, 2000 Issued
Array ( [id] => 1495507 [patent_doc_number] => 06342730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Low-pin-count chip package and manufacturing method thereof' [patent_app_type] => B1 [patent_app_number] => 09/492820 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2863 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/342/06342730.pdf [firstpage_image] =>[orig_patent_app_number] => 09492820 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/492820
Low-pin-count chip package and manufacturing method thereof Jan 27, 2000 Issued
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