Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4163407 [patent_doc_number] => 06114752 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Semiconductor package having lead frame with an exposed base pad' [patent_app_type] => 1 [patent_app_number] => 9/382742 [patent_app_country] => US [patent_app_date] => 1999-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2772 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114752.pdf [firstpage_image] =>[orig_patent_app_number] => 382742 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/382742
Semiconductor package having lead frame with an exposed base pad Aug 24, 1999 Issued
Array ( [id] => 4373591 [patent_doc_number] => 06274933 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Integrated circuit device having a planar interlevel dielectric layer' [patent_app_type] => 1 [patent_app_number] => 9/376233 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2479 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274933.pdf [firstpage_image] =>[orig_patent_app_number] => 376233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376233
Integrated circuit device having a planar interlevel dielectric layer Aug 16, 1999 Issued
Array ( [id] => 1544393 [patent_doc_number] => 06373141 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Bondable compliant pads for packaging of a semiconductor chip and method therefor' [patent_app_type] => B1 [patent_app_number] => 09/375572 [patent_app_country] => US [patent_app_date] => 1999-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 7401 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373141.pdf [firstpage_image] =>[orig_patent_app_number] => 09375572 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/375572
Bondable compliant pads for packaging of a semiconductor chip and method therefor Aug 15, 1999 Issued
Array ( [id] => 4282939 [patent_doc_number] => 06281584 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfaces' [patent_app_type] => 1 [patent_app_number] => 9/373482 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3800 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281584.pdf [firstpage_image] =>[orig_patent_app_number] => 373482 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/373482
Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfaces Aug 11, 1999 Issued
Array ( [id] => 1476427 [patent_doc_number] => 06388332 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Integrated circuit power and ground routing' [patent_app_type] => B1 [patent_app_number] => 09/371371 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4972 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388332.pdf [firstpage_image] =>[orig_patent_app_number] => 09371371 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371371
Integrated circuit power and ground routing Aug 9, 1999 Issued
Array ( [id] => 4334093 [patent_doc_number] => 06320267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Bonding layer in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/369282 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 5782 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320267.pdf [firstpage_image] =>[orig_patent_app_number] => 369282 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/369282
Bonding layer in a semiconductor device Aug 5, 1999 Issued
09/370003 THIN FILM METAL BARRIER FOR ELECTRICAL INTERCONNECTIONS Aug 5, 1999 Abandoned
Array ( [id] => 4366611 [patent_doc_number] => 06255727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Contact structure formed by microfabrication process' [patent_app_type] => 1 [patent_app_number] => 9/368003 [patent_app_country] => US [patent_app_date] => 1999-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 94 [patent_no_of_words] => 13931 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255727.pdf [firstpage_image] =>[orig_patent_app_number] => 368003 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/368003
Contact structure formed by microfabrication process Aug 2, 1999 Issued
Array ( [id] => 4414546 [patent_doc_number] => 06229211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/362683 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 63 [patent_no_of_words] => 17001 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229211.pdf [firstpage_image] =>[orig_patent_app_number] => 362683 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/362683
Semiconductor device and method of manufacturing the same Jul 28, 1999 Issued
Array ( [id] => 4275431 [patent_doc_number] => 06307263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Integrated semiconductor chip with modular dummy structures' [patent_app_type] => 1 [patent_app_number] => 9/363263 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2627 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307263.pdf [firstpage_image] =>[orig_patent_app_number] => 363263 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363263
Integrated semiconductor chip with modular dummy structures Jul 28, 1999 Issued
Array ( [id] => 4413162 [patent_doc_number] => 06239495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Multichip semiconductor device and memory card' [patent_app_type] => 1 [patent_app_number] => 9/363031 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7570 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239495.pdf [firstpage_image] =>[orig_patent_app_number] => 363031 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363031
Multichip semiconductor device and memory card Jul 28, 1999 Issued
Array ( [id] => 4366567 [patent_doc_number] => 06255724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Self-centering arrangement of microstructured elements' [patent_app_type] => 1 [patent_app_number] => 9/297042 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3023 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255724.pdf [firstpage_image] =>[orig_patent_app_number] => 297042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/297042
Self-centering arrangement of microstructured elements Jul 28, 1999 Issued
Array ( [id] => 4351288 [patent_doc_number] => 06285085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Semiconductor device, method of fabricating the same and structure for mounting the same' [patent_app_type] => 1 [patent_app_number] => 9/362110 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 6553 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285085.pdf [firstpage_image] =>[orig_patent_app_number] => 362110 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/362110
Semiconductor device, method of fabricating the same and structure for mounting the same Jul 27, 1999 Issued
Array ( [id] => 1448144 [patent_doc_number] => 06369452 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Cap attach surface modification for improved adhesion' [patent_app_type] => B1 [patent_app_number] => 09/361723 [patent_app_country] => US [patent_app_date] => 1999-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3997 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/369/06369452.pdf [firstpage_image] =>[orig_patent_app_number] => 09361723 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/361723
Cap attach surface modification for improved adhesion Jul 26, 1999 Issued
Array ( [id] => 4310271 [patent_doc_number] => 06326689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Backside contact for touchchip' [patent_app_type] => 1 [patent_app_number] => 9/360802 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326689.pdf [firstpage_image] =>[orig_patent_app_number] => 360802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/360802
Backside contact for touchchip Jul 25, 1999 Issued
Array ( [id] => 4159169 [patent_doc_number] => 06124632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Monolithic silicon mass flow control structure' [patent_app_type] => 1 [patent_app_number] => 9/359423 [patent_app_country] => US [patent_app_date] => 1999-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1424 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124632.pdf [firstpage_image] =>[orig_patent_app_number] => 359423 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/359423
Monolithic silicon mass flow control structure Jul 22, 1999 Issued
Array ( [id] => 1419560 [patent_doc_number] => 06525410 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Integrated circuit wireless tagging' [patent_app_type] => B1 [patent_app_number] => 09/354262 [patent_app_country] => US [patent_app_date] => 1999-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 5187 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525410.pdf [firstpage_image] =>[orig_patent_app_number] => 09354262 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/354262
Integrated circuit wireless tagging Jul 14, 1999 Issued
Array ( [id] => 4361026 [patent_doc_number] => 06218732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Copper bond pad process' [patent_app_type] => 1 [patent_app_number] => 9/354510 [patent_app_country] => US [patent_app_date] => 1999-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1149 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218732.pdf [firstpage_image] =>[orig_patent_app_number] => 354510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/354510
Copper bond pad process Jul 14, 1999 Issued
Array ( [id] => 4351233 [patent_doc_number] => 06285081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Deflectable interconnect' [patent_app_type] => 1 [patent_app_number] => 9/352802 [patent_app_country] => US [patent_app_date] => 1999-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6641 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/285/06285081.pdf [firstpage_image] =>[orig_patent_app_number] => 352802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/352802
Deflectable interconnect Jul 12, 1999 Issued
Array ( [id] => 1442033 [patent_doc_number] => 06335567 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Semiconductor device having stress reducing laminate and method for manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/348830 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 4672 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335567.pdf [firstpage_image] =>[orig_patent_app_number] => 09348830 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/348830
Semiconductor device having stress reducing laminate and method for manufacturing the same Jul 7, 1999 Issued
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