Jasmine Jhihan B. Clark

Array ( [id] => 4189919 [patent_doc_number] => 06150730 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Chip-scale semiconductor package' [patent_app_type] => 1 [patent_app_number] => 9/349231 [patent_app_country] => US [patent_app_date] => 1999-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1901 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150730.pdf [firstpage_image] =>[orig_patent_app_number] => 349231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1566319 [patent_doc_number] => 06339258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Low resistivity tantalum' [patent_app_type] => B1 [patent_app_number] => 09/347221 [patent_app_country] => US [patent_app_date] => 1999-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1712 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339258.pdf [firstpage_image] =>[orig_patent_app_number] => 09347221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4414575 [patent_doc_number] => 06229214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method for fabricating contact electrode of the semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/339842 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 4912 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229214.pdf [firstpage_image] =>[orig_patent_app_number] => 339842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4278246 [patent_doc_number] => 06323549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Ceramic composite wiring structures for semiconductor devices and method of manufacture' [patent_app_type] => 1 [patent_app_number] => 9/344682 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7777 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323549.pdf [firstpage_image] =>[orig_patent_app_number] => 344682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4362840 [patent_doc_number] => 06175152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/338803 [patent_app_country] => US [patent_app_date] => 1999-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6242 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175152.pdf [firstpage_image] =>[orig_patent_app_number] => 338803 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1568465 [patent_doc_number] => 06376910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Solder-on back metal for semiconductor die' [patent_app_type] => B1 [patent_app_number] => 09/361633 [patent_app_country] => US [patent_app_date] => 1999-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1693 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376910.pdf [firstpage_image] =>[orig_patent_app_number] => 09361633 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4390255 [patent_doc_number] => 06262487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method' [patent_app_type] => 1 [patent_app_number] => 9/338593 [patent_app_country] => US [patent_app_date] => 1999-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 49 [patent_no_of_words] => 13044 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262487.pdf [firstpage_image] =>[orig_patent_app_number] => 338593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4190576 [patent_doc_number] => 06160296 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Titanium nitride interconnects' [patent_app_type] => 1 [patent_app_number] => 9/338211 [patent_app_country] => US [patent_app_date] => 1999-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4792 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/160/06160296.pdf [firstpage_image] =>[orig_patent_app_number] => 338211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4413010 [patent_doc_number] => 06239482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Integrated circuit package including window frame' [patent_app_type] => 1 [patent_app_number] => 9/334572 [patent_app_country] => US [patent_app_date] => 1999-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3417 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239482.pdf [firstpage_image] =>[orig_patent_app_number] => 334572 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4361079 [patent_doc_number] => 06218736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Circuit board and semiconductor device, and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/332968 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 3612 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218736.pdf [firstpage_image] =>[orig_patent_app_number] => 332968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1587930 [patent_doc_number] => 06359334 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Thermally conductive adhesive tape for semiconductor devices and method using the same' [patent_app_type] => B1 [patent_app_number] => 09/327692 [patent_app_country] => US [patent_app_date] => 1999-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2435 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359334.pdf [firstpage_image] =>[orig_patent_app_number] => 09327692 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4089858 [patent_doc_number] => 06163076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Stacked structure of semiconductor package' [patent_app_type] => 1 [patent_app_number] => 9/325382 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1839 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163076.pdf [firstpage_image] =>[orig_patent_app_number] => 325382 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424822 [patent_doc_number] => 06225692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Flip chip package for micromachined semiconductors' [patent_app_type] => 1 [patent_app_number] => 9/325282 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2737 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225692.pdf [firstpage_image] =>[orig_patent_app_number] => 325282 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4132694 [patent_doc_number] => 06127726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Cavity down plastic ball grid array multi-chip module' [patent_app_type] => 1 [patent_app_number] => 9/321298 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4607 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127726.pdf [firstpage_image] =>[orig_patent_app_number] => 321298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4385899 [patent_doc_number] => 06303991 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Electronic package and contact therefor' [patent_app_type] => 1 [patent_app_number] => 9/321320 [patent_app_country] => US [patent_app_date] => 1999-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3862 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303991.pdf [firstpage_image] =>[orig_patent_app_number] => 321320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4253622 [patent_doc_number] => 06137174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Hybrid ASIC/memory module package' [patent_app_type] => 1 [patent_app_number] => 9/318943 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1344 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137174.pdf [firstpage_image] =>[orig_patent_app_number] => 318943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1603256 [patent_doc_number] => 06433436 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Dual-RIE structure for via/line interconnections' [patent_app_type] => B1 [patent_app_number] => 09/320612 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 4443 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/433/06433436.pdf [firstpage_image] =>[orig_patent_app_number] => 09320612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4385885 [patent_doc_number] => 06303990 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Conductor path contacting arrangement and method' [patent_app_type] => 1 [patent_app_number] => 9/320603 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2306 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303990.pdf [firstpage_image] =>[orig_patent_app_number] => 320603 [rel_patent_id] =>[rel_patent_doc_number] =>)