Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4275577 [patent_doc_number] => 06307272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/317853 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 70 [patent_no_of_words] => 17493 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307272.pdf [firstpage_image] =>[orig_patent_app_number] => 317853 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/317853
Semiconductor device and method for manufacturing the same May 24, 1999 Issued
Array ( [id] => 4102263 [patent_doc_number] => 06097102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Reticle, semiconductor wafer, and semiconductor chip' [patent_app_type] => 1 [patent_app_number] => 9/315842 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3424 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097102.pdf [firstpage_image] =>[orig_patent_app_number] => 315842 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315842
Reticle, semiconductor wafer, and semiconductor chip May 20, 1999 Issued
Array ( [id] => 4364744 [patent_doc_number] => 06191473 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Bonding lead structure with enhanced encapsulation' [patent_app_type] => 1 [patent_app_number] => 9/315252 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7308 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191473.pdf [firstpage_image] =>[orig_patent_app_number] => 315252 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/315252
Bonding lead structure with enhanced encapsulation May 19, 1999 Issued
Array ( [id] => 4244378 [patent_doc_number] => 06166446 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Semiconductor device and fabrication process thereof' [patent_app_type] => 1 [patent_app_number] => 9/180932 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3542 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166446.pdf [firstpage_image] =>[orig_patent_app_number] => 180932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/180932
Semiconductor device and fabrication process thereof May 17, 1999 Issued
Array ( [id] => 4108738 [patent_doc_number] => 06100591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/314582 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5843 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100591.pdf [firstpage_image] =>[orig_patent_app_number] => 314582 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314582
Semiconductor device and method of fabricating the same May 17, 1999 Issued
Array ( [id] => 4355588 [patent_doc_number] => 06215176 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Dual leadframe package' [patent_app_type] => 1 [patent_app_number] => 9/313171 [patent_app_country] => US [patent_app_date] => 1999-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2158 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215176.pdf [firstpage_image] =>[orig_patent_app_number] => 313171 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313171
Dual leadframe package May 16, 1999 Issued
Array ( [id] => 4424773 [patent_doc_number] => 06225683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Die size-increasing integrated circuit leads and thermally enhanced leadframe' [patent_app_type] => 1 [patent_app_number] => 9/312142 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 4029 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225683.pdf [firstpage_image] =>[orig_patent_app_number] => 312142 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/312142
Die size-increasing integrated circuit leads and thermally enhanced leadframe May 13, 1999 Issued
Array ( [id] => 4038579 [patent_doc_number] => 05994785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Epoxy resin compositions and semiconductor devices encapsulated therewith' [patent_app_type] => 1 [patent_app_number] => 9/305453 [patent_app_country] => US [patent_app_date] => 1999-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4346 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994785.pdf [firstpage_image] =>[orig_patent_app_number] => 305453 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/305453
Epoxy resin compositions and semiconductor devices encapsulated therewith May 5, 1999 Issued
Array ( [id] => 1328366 [patent_doc_number] => 06603209 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Compliant integrated circuit package' [patent_app_type] => B1 [patent_app_number] => 09/306623 [patent_app_country] => US [patent_app_date] => 1999-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 8503 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/603/06603209.pdf [firstpage_image] =>[orig_patent_app_number] => 09306623 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/306623
Compliant integrated circuit package May 5, 1999 Issued
Array ( [id] => 1524909 [patent_doc_number] => 06353261 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Method and apparatus for reducing interconnect resistance using an interconnect well' [patent_app_type] => B1 [patent_app_number] => 09/303891 [patent_app_country] => US [patent_app_date] => 1999-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5311 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353261.pdf [firstpage_image] =>[orig_patent_app_number] => 09303891 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/303891
Method and apparatus for reducing interconnect resistance using an interconnect well May 2, 1999 Issued
Array ( [id] => 4355789 [patent_doc_number] => 06215189 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Semiconductor device having interconnect layer and method of manufacturing therefor' [patent_app_type] => 1 [patent_app_number] => 9/302290 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 9528 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215189.pdf [firstpage_image] =>[orig_patent_app_number] => 302290 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302290
Semiconductor device having interconnect layer and method of manufacturing therefor Apr 29, 1999 Issued
Array ( [id] => 4140867 [patent_doc_number] => 06016011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Method and apparatus for a dual-inlaid damascene contact to sensor' [patent_app_type] => 1 [patent_app_number] => 9/300812 [patent_app_country] => US [patent_app_date] => 1999-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 20 [patent_no_of_words] => 4828 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016011.pdf [firstpage_image] =>[orig_patent_app_number] => 300812 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/300812
Method and apparatus for a dual-inlaid damascene contact to sensor Apr 26, 1999 Issued
Array ( [id] => 4223006 [patent_doc_number] => 06087714 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Semiconductor devices having tin-based solder film containing no lead and process for producing the devices' [patent_app_type] => 1 [patent_app_number] => 9/298841 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5573 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087714.pdf [firstpage_image] =>[orig_patent_app_number] => 298841 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298841
Semiconductor devices having tin-based solder film containing no lead and process for producing the devices Apr 25, 1999 Issued
Array ( [id] => 4423814 [patent_doc_number] => 06177733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/295333 [patent_app_country] => US [patent_app_date] => 1999-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6429 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177733.pdf [firstpage_image] =>[orig_patent_app_number] => 295333 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295333
Semiconductor device Apr 20, 1999 Issued
Array ( [id] => 4309957 [patent_doc_number] => 06188135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Copper interconnect with top barrier layer' [patent_app_type] => 1 [patent_app_number] => 9/294047 [patent_app_country] => US [patent_app_date] => 1999-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1946 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188135.pdf [firstpage_image] =>[orig_patent_app_number] => 294047 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/294047
Copper interconnect with top barrier layer Apr 18, 1999 Issued
Array ( [id] => 4294449 [patent_doc_number] => 06211574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Semiconductor package with wire protection and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/292742 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2412 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211574.pdf [firstpage_image] =>[orig_patent_app_number] => 292742 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/292742
Semiconductor package with wire protection and method therefor Apr 15, 1999 Issued
Array ( [id] => 4390269 [patent_doc_number] => 06262488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Semiconductor memory module having double-sided memory chip layout' [patent_app_type] => 1 [patent_app_number] => 9/292999 [patent_app_country] => US [patent_app_date] => 1999-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 48 [patent_no_of_words] => 10118 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262488.pdf [firstpage_image] =>[orig_patent_app_number] => 292999 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/292999
Semiconductor memory module having double-sided memory chip layout Apr 15, 1999 Issued
Array ( [id] => 4411063 [patent_doc_number] => 06271596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Damascene capacitors for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/292422 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271596.pdf [firstpage_image] =>[orig_patent_app_number] => 292422 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/292422
Damascene capacitors for integrated circuits Apr 14, 1999 Issued
Array ( [id] => 4266160 [patent_doc_number] => 06259155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Polymer enhanced column grid array' [patent_app_type] => 1 [patent_app_number] => 9/290311 [patent_app_country] => US [patent_app_date] => 1999-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2368 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259155.pdf [firstpage_image] =>[orig_patent_app_number] => 290311 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/290311
Polymer enhanced column grid array Apr 11, 1999 Issued
Array ( [id] => 4334065 [patent_doc_number] => 06320265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Semiconductor device with high-temperature ohmic contact and method of forming the same' [patent_app_type] => 1 [patent_app_number] => 9/290535 [patent_app_country] => US [patent_app_date] => 1999-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3753 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320265.pdf [firstpage_image] =>[orig_patent_app_number] => 290535 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/290535
Semiconductor device with high-temperature ohmic contact and method of forming the same Apr 11, 1999 Issued
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