Jasmine Jhihan B. Clark

Array ( [id] => 4411902 [patent_doc_number] => 06172413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Chip leads constrained in dielectric media' [patent_app_type] => 1 [patent_app_number] => 8/948120 [patent_app_country] => US [patent_app_date] => 1997-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5887 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172413.pdf [firstpage_image] =>[orig_patent_app_number] => 948120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4161628 [patent_doc_number] => 06107690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Coated semiconductor die/leadframe assembly and method for coating the assembly' [patent_app_type] => 1 [patent_app_number] => 8/947011 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1980 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107690.pdf [firstpage_image] =>[orig_patent_app_number] => 947011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3909389 [patent_doc_number] => 05898223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Chip-on-chip IC packages' [patent_app_type] => 1 [patent_app_number] => 8/946980 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3922 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898223.pdf [firstpage_image] =>[orig_patent_app_number] => 946980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4108752 [patent_doc_number] => 06100592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Integrated circuitry and method of forming a contact landing pad' [patent_app_type] => 1 [patent_app_number] => 8/946034 [patent_app_country] => US [patent_app_date] => 1997-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2161 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100592.pdf [firstpage_image] =>[orig_patent_app_number] => 946034 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4009665 [patent_doc_number] => 06005286 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Increasing the gap between a lead frame and a semiconductor die' [patent_app_type] => 1 [patent_app_number] => 8/944743 [patent_app_country] => US [patent_app_date] => 1997-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2324 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/005/06005286.pdf [firstpage_image] =>[orig_patent_app_number] => 944743 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4017520 [patent_doc_number] => 05962926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Semiconductor device having multiple overlapping rows of bond pads with conductive interconnects and method of pad placement' [patent_app_type] => 1 [patent_app_number] => 8/940605 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3549 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/962/05962926.pdf [firstpage_image] =>[orig_patent_app_number] => 940605 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4049218 [patent_doc_number] => 05909058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Semiconductor package and semiconductor mounting part' [patent_app_type] => 1 [patent_app_number] => 8/934775 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6494 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909058.pdf [firstpage_image] =>[orig_patent_app_number] => 934775 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4022276 [patent_doc_number] => 05907185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Ceramic terminal block, hermetic sealed package, and complex semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/934889 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4765 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907185.pdf [firstpage_image] =>[orig_patent_app_number] => 934889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3892327 [patent_doc_number] => 05894166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Chip mounting scheme' [patent_app_type] => 1 [patent_app_number] => 8/932709 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894166.pdf [firstpage_image] =>[orig_patent_app_number] => 932709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4013832 [patent_doc_number] => 05889333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Semiconductor device and method for manufacturing such' [patent_app_type] => 1 [patent_app_number] => 8/925067 [patent_app_country] => US [patent_app_date] => 1997-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 32 [patent_no_of_words] => 5816 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889333.pdf [firstpage_image] =>[orig_patent_app_number] => 925067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4056564 [patent_doc_number] => 05969425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Borderless vias with CVD barrier layer' [patent_app_type] => 1 [patent_app_number] => 8/924131 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3782 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969425.pdf [firstpage_image] =>[orig_patent_app_number] => 924131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3954226 [patent_doc_number] => 05977623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Semiconductor package and socket thereof and methods of fabricating same' [patent_app_type] => 1 [patent_app_number] => 8/919175 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2285 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977623.pdf [firstpage_image] =>[orig_patent_app_number] => 919175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3865290 [patent_doc_number] => 05793118 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Semiconductor device capable of accomplishing a high moisture proof' [patent_app_type] => 1 [patent_app_number] => 8/916824 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5773 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793118.pdf [firstpage_image] =>[orig_patent_app_number] => 916824 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4003077 [patent_doc_number] => 05986333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Semiconductor apparatus and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 8/916445 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 4906 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986333.pdf [firstpage_image] =>[orig_patent_app_number] => 916445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4140890 [patent_doc_number] => 06016013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Semiconductor device mounting structure' [patent_app_type] => 1 [patent_app_number] => 8/915272 [patent_app_country] => US [patent_app_date] => 1997-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4654 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016013.pdf [firstpage_image] =>[orig_patent_app_number] => 915272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4013655 [patent_doc_number] => 05889323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Semiconductor package and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/912788 [patent_app_country] => US [patent_app_date] => 1997-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 1974 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889323.pdf [firstpage_image] =>[orig_patent_app_number] => 912788 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3989990 [patent_doc_number] => 05959348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Construction of PBGA substrate for flip chip packing' [patent_app_type] => 1 [patent_app_number] => 8/912271 [patent_app_country] => US [patent_app_date] => 1997-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5073 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959348.pdf [firstpage_image] =>[orig_patent_app_number] => 912271 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3892386 [patent_doc_number] => 05894170 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Wiring layer in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/912067 [patent_app_country] => US [patent_app_date] => 1997-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 6133 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894170.pdf [firstpage_image] =>[orig_patent_app_number] => 912067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4013590 [patent_doc_number] => 05889318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Lead frame including angle iron tie bar and method of making the same' [patent_app_type] => 1 [patent_app_number] => 8/909931 [patent_app_country] => US [patent_app_date] => 1997-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2753 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889318.pdf [firstpage_image] =>[orig_patent_app_number] => 909931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3939215 [patent_doc_number] => 05939780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Power supply circuit for a semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/907923 [patent_app_country] => US [patent_app_date] => 1997-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3601 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/939/05939780.pdf [firstpage_image] =>[orig_patent_app_number] => 907923 [rel_patent_id] =>[rel_patent_doc_number] =>)