
Jasmine Jhihan B. Clark
Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815, 2899, 3621, 2816, 2503 |
| Total Applications | 3065 |
| Issued Applications | 2831 |
| Pending Applications | 98 |
| Abandoned Applications | 163 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18277079
[patent_doc_number] => 11616027
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-28
[patent_title] => Integrated circuit packages to minimize stress on a semiconductor die
[patent_app_type] => utility
[patent_app_number] => 16/951720
[patent_app_country] => US
[patent_app_date] => 2020-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 26871
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16951720
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/951720 | Integrated circuit packages to minimize stress on a semiconductor die | Nov 17, 2020 | Issued |
Array
(
[id] => 17025505
[patent_doc_number] => 20210249377
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-12
[patent_title] => SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 16/950211
[patent_app_country] => US
[patent_app_date] => 2020-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9469
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950211
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/950211 | Semiconductor package | Nov 16, 2020 | Issued |
Array
(
[id] => 18736846
[patent_doc_number] => 11805602
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-31
[patent_title] => Chip assemblies
[patent_app_type] => utility
[patent_app_number] => 17/089736
[patent_app_country] => US
[patent_app_date] => 2020-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 16713
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089736
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/089736 | Chip assemblies | Nov 4, 2020 | Issued |
Array
(
[id] => 16765503
[patent_doc_number] => 20210111085
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-15
[patent_title] => SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/081029
[patent_app_country] => US
[patent_app_date] => 2020-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9278
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081029
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/081029 | Semiconductor device and a method of manufacturing a semiconductor device | Oct 26, 2020 | Issued |
Array
(
[id] => 16617406
[patent_doc_number] => 20210036059
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-04
[patent_title] => INTEGRATED CIRCUIT (IC) PACKAGE WITH INTEGRATED INDUCTOR HAVING CORE MAGNETIC FIELD (B FIELD) EXTENDING PARALLEL TO DIE SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 17/074848
[patent_app_country] => US
[patent_app_date] => 2020-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14778
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074848
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/074848 | Integrated circuit (IC) package with integrated inductor having core magnetic field (B field) extending parallel to substrate | Oct 19, 2020 | Issued |
Array
(
[id] => 17536729
[patent_doc_number] => 20220115338
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-14
[patent_title] => SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/067556
[patent_app_country] => US
[patent_app_date] => 2020-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4454
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17067556
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/067556 | Semiconductor device package and method of manufacturing the same | Oct 8, 2020 | Issued |
Array
(
[id] => 18357864
[patent_doc_number] => 11646270
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-05-09
[patent_title] => Multi-chip package and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/065521
[patent_app_country] => US
[patent_app_date] => 2020-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5957
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17065521
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/065521 | Multi-chip package and manufacturing method thereof | Oct 7, 2020 | Issued |
Array
(
[id] => 18131348
[patent_doc_number] => 11557565
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-17
[patent_title] => Semiconductor device assembly and method therefor
[patent_app_type] => utility
[patent_app_number] => 17/063763
[patent_app_country] => US
[patent_app_date] => 2020-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3985
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17063763
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/063763 | Semiconductor device assembly and method therefor | Oct 5, 2020 | Issued |
Array
(
[id] => 17048063
[patent_doc_number] => 11101253
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-08-24
[patent_title] => Semiconductor package
[patent_app_type] => utility
[patent_app_number] => 17/036053
[patent_app_country] => US
[patent_app_date] => 2020-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 5546
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036053
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/036053 | Semiconductor package | Sep 28, 2020 | Issued |
Array
(
[id] => 17174160
[patent_doc_number] => 20210327831
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-21
[patent_title] => SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP AND CAPACITOR
[patent_app_type] => utility
[patent_app_number] => 17/031102
[patent_app_country] => US
[patent_app_date] => 2020-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4128
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 30
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17031102
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/031102 | Semiconductor package including semiconductor chip and capacitor | Sep 23, 2020 | Issued |
Array
(
[id] => 18431711
[patent_doc_number] => 11676941
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-13
[patent_title] => Semiconductor package and fabricating method thereof
[patent_app_type] => utility
[patent_app_number] => 17/028621
[patent_app_country] => US
[patent_app_date] => 2020-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 52
[patent_figures_cnt] => 94
[patent_no_of_words] => 36945
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028621
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/028621 | Semiconductor package and fabricating method thereof | Sep 21, 2020 | Issued |
Array
(
[id] => 17477473
[patent_doc_number] => 20220084977
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-17
[patent_title] => EDGE-NOTCHED SUBSTRATE PACKAGING AND ASSOCIATED SYSTEMS AND METHODS
[patent_app_type] => utility
[patent_app_number] => 17/023143
[patent_app_country] => US
[patent_app_date] => 2020-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3746
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17023143
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/023143 | Edge-notched substrate packaging and associated systems and methods | Sep 15, 2020 | Issued |
Array
(
[id] => 16677600
[patent_doc_number] => 20210066366
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-04
[patent_title] => NOVEL IMAGE SENSOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/020454
[patent_app_country] => US
[patent_app_date] => 2020-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5284
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17020454
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/020454 | Image sensor device | Sep 13, 2020 | Issued |
Array
(
[id] => 16544952
[patent_doc_number] => 20200411367
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-31
[patent_title] => SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/019343
[patent_app_country] => US
[patent_app_date] => 2020-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3654
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17019343
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/019343 | Semiconductor structure | Sep 12, 2020 | Issued |
Array
(
[id] => 16578733
[patent_doc_number] => 20210013134
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-14
[patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE AND CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 17/015619
[patent_app_country] => US
[patent_app_date] => 2020-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5720
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17015619
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/015619 | Method of manufacturing semiconductor devices, corresponding device and circuit | Sep 8, 2020 | Issued |
Array
(
[id] => 17463745
[patent_doc_number] => 20220077051
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-10
[patent_title] => PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/015012
[patent_app_country] => US
[patent_app_date] => 2020-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2132
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17015012
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/015012 | Package structure and manufacturing method thereof | Sep 7, 2020 | Issued |
Array
(
[id] => 17716647
[patent_doc_number] => 11380646
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-05
[patent_title] => Multi-sided cooling semiconductor package and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 17/012075
[patent_app_country] => US
[patent_app_date] => 2020-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 5132
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17012075
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/012075 | Multi-sided cooling semiconductor package and method of manufacturing the same | Sep 3, 2020 | Issued |
Array
(
[id] => 18507615
[patent_doc_number] => 11705443
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-18
[patent_title] => Semiconductor memory device
[patent_app_type] => utility
[patent_app_number] => 17/012111
[patent_app_country] => US
[patent_app_date] => 2020-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 25
[patent_no_of_words] => 16063
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17012111
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/012111 | Semiconductor memory device | Sep 3, 2020 | Issued |
Array
(
[id] => 18999152
[patent_doc_number] => 11916008
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-27
[patent_title] => Chip-on-film packaging structure and chip-on-film packaging method
[patent_app_type] => utility
[patent_app_number] => 17/261756
[patent_app_country] => US
[patent_app_date] => 2020-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2448
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17261756
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/261756 | Chip-on-film packaging structure and chip-on-film packaging method | Sep 2, 2020 | Issued |
Array
(
[id] => 16873574
[patent_doc_number] => 20210167041
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-03
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/011487
[patent_app_country] => US
[patent_app_date] => 2020-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11789
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17011487
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/011487 | Semiconductor memory device | Sep 2, 2020 | Issued |