Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16536594 [patent_doc_number] => 10879207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Bonded structures [patent_app_type] => utility [patent_app_number] => 16/724017 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 34 [patent_no_of_words] => 11267 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724017 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/724017
Bonded structures Dec 19, 2019 Issued
Array ( [id] => 18857336 [patent_doc_number] => 11854931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => STIM/liquid metal filled laser drill trench to improve cooling of stacked bottom die [patent_app_type] => utility [patent_app_number] => 16/721807 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 10389 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721807 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/721807
STIM/liquid metal filled laser drill trench to improve cooling of stacked bottom die Dec 18, 2019 Issued
Array ( [id] => 17152471 [patent_doc_number] => 11145562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Package structure and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/721829 [patent_app_country] => US [patent_app_date] => 2019-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 8056 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16721829 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/721829
Package structure and method of manufacturing the same Dec 18, 2019 Issued
Array ( [id] => 18205512 [patent_doc_number] => 11587918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Semiconductor devices, semiconductor device packages, electronic systems including same, and related methods [patent_app_type] => utility [patent_app_number] => 16/717827 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7775 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717827 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/717827
Semiconductor devices, semiconductor device packages, electronic systems including same, and related methods Dec 16, 2019 Issued
Array ( [id] => 18205512 [patent_doc_number] => 11587918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Semiconductor devices, semiconductor device packages, electronic systems including same, and related methods [patent_app_type] => utility [patent_app_number] => 16/717827 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7775 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717827 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/717827
Semiconductor devices, semiconductor device packages, electronic systems including same, and related methods Dec 16, 2019 Issued
Array ( [id] => 18205512 [patent_doc_number] => 11587918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Semiconductor devices, semiconductor device packages, electronic systems including same, and related methods [patent_app_type] => utility [patent_app_number] => 16/717827 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7775 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717827 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/717827
Semiconductor devices, semiconductor device packages, electronic systems including same, and related methods Dec 16, 2019 Issued
Array ( [id] => 18205512 [patent_doc_number] => 11587918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Semiconductor devices, semiconductor device packages, electronic systems including same, and related methods [patent_app_type] => utility [patent_app_number] => 16/717827 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7775 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717827 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/717827
Semiconductor devices, semiconductor device packages, electronic systems including same, and related methods Dec 16, 2019 Issued
Array ( [id] => 18529890 [patent_doc_number] => 11716907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-01 [patent_title] => Electromechanical microsystem comprising an active element having a structured core layer [patent_app_type] => utility [patent_app_number] => 16/717866 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3655 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717866 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/717866
Electromechanical microsystem comprising an active element having a structured core layer Dec 16, 2019 Issued
Array ( [id] => 15775843 [patent_doc_number] => 20200118939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => WIRE BOND WIRES FOR INTERFERENCE SHIELDING [patent_app_type] => utility [patent_app_number] => 16/715524 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715524 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715524
Wire bond wires for interference shielding Dec 15, 2019 Issued
Array ( [id] => 16987969 [patent_doc_number] => 11075152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 16/715697 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 11191 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715697 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715697
Semiconductor package Dec 15, 2019 Issued
Array ( [id] => 17254092 [patent_doc_number] => 11189590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Processes for adjusting dimensions of dielectric bond line materials and related films, articles and assemblies [patent_app_type] => utility [patent_app_number] => 16/715594 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715594 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/715594
Processes for adjusting dimensions of dielectric bond line materials and related films, articles and assemblies Dec 15, 2019 Issued
Array ( [id] => 16904892 [patent_doc_number] => 20210183808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SENSOR SYSTEMS AND METHODS FOR PROVIDING SENSOR SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/713437 [patent_app_country] => US [patent_app_date] => 2019-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16713437 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/713437
Sensor systems and methods for providing sensor systems Dec 12, 2019 Issued
Array ( [id] => 15840681 [patent_doc_number] => 20200135623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => QFN PRE-MOLDED LEADFRAME HAVING A SOLDER WETTABLE SIDEWALL ON EACH LEAD [patent_app_type] => utility [patent_app_number] => 16/712789 [patent_app_country] => US [patent_app_date] => 2019-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16712789 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/712789
QFN pre-molded leadframe having a solder wettable sidewall on each lead Dec 11, 2019 Issued
Array ( [id] => 15748307 [patent_doc_number] => 20200113043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => HIGH-CURRENT PCB TRACES [patent_app_type] => utility [patent_app_number] => 16/704540 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704540 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704540
High-current PCB traces Dec 4, 2019 Issued
Array ( [id] => 15745681 [patent_doc_number] => 20200111730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/703460 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7084 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703460 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703460
Semiconductor package Dec 3, 2019 Issued
Array ( [id] => 16888977 [patent_doc_number] => 20210175174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => Cu-Cu Bonding for Interconnects on Bridge Chip Attached to Chips and Packaging Substrate [patent_app_type] => utility [patent_app_number] => 16/703252 [patent_app_country] => US [patent_app_date] => 2019-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16703252 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/703252
Cu--Cu bonding for interconnects on bridge chip attached to chips and packaging substrate Dec 3, 2019 Issued
Array ( [id] => 16448268 [patent_doc_number] => 10840199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Methods of forming connector pad structures, interconnect structures, and structures thereof [patent_app_type] => utility [patent_app_number] => 16/701513 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 9097 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16701513 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/701513
Methods of forming connector pad structures, interconnect structures, and structures thereof Dec 2, 2019 Issued
Array ( [id] => 16324260 [patent_doc_number] => 10784232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Semiconductor package and fabricating method thereof [patent_app_type] => utility [patent_app_number] => 16/700592 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 66 [patent_no_of_words] => 29359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16700592 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/700592
Semiconductor package and fabricating method thereof Dec 1, 2019 Issued
Array ( [id] => 15684297 [patent_doc_number] => 20200096812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/698281 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16698281 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/698281
DISPLAY DEVICE Nov 26, 2019 Abandoned
Array ( [id] => 15688083 [patent_doc_number] => 20200098705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => Wafer Level Package (WLP) and Method for Forming the Same [patent_app_type] => utility [patent_app_number] => 16/696771 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16696771 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/696771
Wafer level package (WLP) and method for forming the same Nov 25, 2019 Issued
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