Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16858469 [patent_doc_number] => 20210159214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => STACKED DIE PACKAGE WITH CURVED SPACER [patent_app_type] => utility [patent_app_number] => 16/692652 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692652 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692652
Stacked die package with curved spacer Nov 21, 2019 Issued
Array ( [id] => 15660917 [patent_doc_number] => 20200092989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => PRINTED CIRCUIT BOARD INCLUDING WARPAGE OFFSET REGIONS AND SEMICONDUCTOR PACKAGES INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/689403 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689403 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/689403
Printed circuit board including warpage offset regions and semiconductor packages including the same Nov 19, 2019 Issued
Array ( [id] => 15939291 [patent_doc_number] => 20200161279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => Component Carrier and Method of Manufacturing the Same [patent_app_type] => utility [patent_app_number] => 16/689213 [patent_app_country] => US [patent_app_date] => 2019-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16689213 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/689213
Component carrier and method of manufacturing the same Nov 19, 2019 Issued
Array ( [id] => 17289071 [patent_doc_number] => 11205632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-21 [patent_title] => Wiring substrate and semiconductor device [patent_app_type] => utility [patent_app_number] => 16/683651 [patent_app_country] => US [patent_app_date] => 2019-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 12938 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16683651 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/683651
Wiring substrate and semiconductor device Nov 13, 2019 Issued
Array ( [id] => 16827819 [patent_doc_number] => 20210143112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/681329 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16681329 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/681329
Semiconductor device Nov 11, 2019 Issued
Array ( [id] => 16425090 [patent_doc_number] => 20200350288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/680657 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16680657 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/680657
Semiconductor package Nov 11, 2019 Issued
Array ( [id] => 17018435 [patent_doc_number] => 11088080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Chip package structure using silicon interposer as interconnection bridge [patent_app_type] => utility [patent_app_number] => 16/679326 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2593 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16679326 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/679326
Chip package structure using silicon interposer as interconnection bridge Nov 10, 2019 Issued
Array ( [id] => 16827836 [patent_doc_number] => 20210143129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => SEMICONDUCTOR MODULE, DIMM MODULE, MANUFACTURING METHOD OF SEMICONDUCTOR MODULE, AND MANUFACTURING METHOD OF DIMM MODULE [patent_app_type] => utility [patent_app_number] => 16/962312 [patent_app_country] => US [patent_app_date] => 2019-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16962312 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/962312
Semiconductor module, DIMM module, manufacturing method of semiconductor module, and manufacturing method of DIMM module Nov 10, 2019 Issued
Array ( [id] => 17196074 [patent_doc_number] => 11164841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/672581 [patent_app_country] => US [patent_app_date] => 2019-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6062 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16672581 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/672581
Semiconductor device Nov 3, 2019 Issued
Array ( [id] => 16814360 [patent_doc_number] => 20210136915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => OXIDE LINER STRESS BUFFER [patent_app_type] => utility [patent_app_number] => 16/671468 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671468 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/671468
Oxide liner stress buffer Oct 31, 2019 Issued
Array ( [id] => 16812194 [patent_doc_number] => 20210134749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => Integrated Circuit Package and Method [patent_app_type] => utility [patent_app_number] => 16/670277 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670277 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/670277
Integrated circuit package and method Oct 30, 2019 Issued
Array ( [id] => 16264618 [patent_doc_number] => 10756064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Manufacturing method of semiconductor package [patent_app_type] => utility [patent_app_number] => 16/597474 [patent_app_country] => US [patent_app_date] => 2019-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6173 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16597474 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/597474
Manufacturing method of semiconductor package Oct 8, 2019 Issued
Array ( [id] => 18000950 [patent_doc_number] => 11502061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Semiconductor package [patent_app_type] => utility [patent_app_number] => 16/592897 [patent_app_country] => US [patent_app_date] => 2019-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 31 [patent_no_of_words] => 8900 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16592897 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/592897
Semiconductor package Oct 3, 2019 Issued
Array ( [id] => 15745749 [patent_doc_number] => 20200111764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => SEMICONDUCTOR MODULE INCLUDING MEMORY STACK HAVING TSVS [patent_app_type] => utility [patent_app_number] => 16/586321 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586321 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586321
Semiconductor module including memory stack having TSVs Sep 26, 2019 Issued
Array ( [id] => 17925972 [patent_doc_number] => 11469235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Semiconductor device and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/585598 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 9697 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585598 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585598
Semiconductor device and method for fabricating the same Sep 26, 2019 Issued
Array ( [id] => 17310186 [patent_doc_number] => 11211313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Lead frame array for carrying chips and LED package structure with multiple chips [patent_app_type] => utility [patent_app_number] => 16/586442 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4492 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586442 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586442
Lead frame array for carrying chips and LED package structure with multiple chips Sep 26, 2019 Issued
Array ( [id] => 17002627 [patent_doc_number] => 11081450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Radiation shield around a component on a substrate [patent_app_type] => utility [patent_app_number] => 16/585052 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 34 [patent_no_of_words] => 9886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585052 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585052
Radiation shield around a component on a substrate Sep 26, 2019 Issued
Array ( [id] => 16731241 [patent_doc_number] => 20210098389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR PREPARING THE SAME [patent_app_type] => utility [patent_app_number] => 16/585414 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6903 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585414 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585414
Semiconductor device with air gap and method for preparing the same Sep 26, 2019 Issued
Array ( [id] => 16731201 [patent_doc_number] => 20210098349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => INTERCONNECTION WITH SIDE CONNECTION TO SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/585299 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585299 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585299
Interconnection with side connection to substrate Sep 26, 2019 Issued
Array ( [id] => 16731274 [patent_doc_number] => 20210098422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => COMPOSITE IC CHIPS INCLUDING A CHIPLET EMBEDDED WITHIN METALLIZATION LAYERS OF A HOST IC CHIP [patent_app_type] => utility [patent_app_number] => 16/586145 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16586145 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/586145
Composite IC chips including a chiplet embedded within metallization layers of a host IC chip Sep 26, 2019 Issued
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