Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17500711 [patent_doc_number] => 11289421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Methods and structures for improved electrical contact between bonded integrated circuit interfaces [patent_app_type] => utility [patent_app_number] => 16/584666 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 9977 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584666 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/584666
Methods and structures for improved electrical contact between bonded integrated circuit interfaces Sep 25, 2019 Issued
Array ( [id] => 15415075 [patent_doc_number] => 20200027860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => SEAL-RING STRUCTURE FOR STACKING INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/584689 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584689 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/584689
Seal-ring structure for stacking integrated circuits Sep 25, 2019 Issued
Array ( [id] => 17077986 [patent_doc_number] => 11114401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Bonding structure and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/584331 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6506 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584331 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/584331
Bonding structure and method for manufacturing the same Sep 25, 2019 Issued
Array ( [id] => 16773966 [patent_doc_number] => 10985087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Wiring board [patent_app_type] => utility [patent_app_number] => 16/583959 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5032 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16583959 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/583959
Wiring board Sep 25, 2019 Issued
Array ( [id] => 16865807 [patent_doc_number] => 11024560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/583290 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2062 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16583290 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/583290
Semiconductor structure and manufacturing method thereof Sep 25, 2019 Issued
Array ( [id] => 15351643 [patent_doc_number] => 20200013713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => STRUCTURE AND METHOD FOR IMPROVING HIGH VOLTAGE BREAKDOWN RELIABILITY OF A MICROELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/572346 [patent_app_country] => US [patent_app_date] => 2019-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16572346 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/572346
Structure and method for improving high voltage breakdown reliability of a microelectronic device Sep 15, 2019 Issued
Array ( [id] => 15332265 [patent_doc_number] => 20200006462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/567017 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16567017 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/567017
Display device Sep 10, 2019 Issued
Array ( [id] => 16699913 [patent_doc_number] => 10950521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Thermal interface material layer and package-on-package device including the same [patent_app_type] => utility [patent_app_number] => 16/566380 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 8398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566380 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566380
Thermal interface material layer and package-on-package device including the same Sep 9, 2019 Issued
Array ( [id] => 15332465 [patent_doc_number] => 20200006562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => INVERTED LEADS FOR PACKAGED ISOLATION DEVICES [patent_app_type] => utility [patent_app_number] => 16/566187 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566187 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566187
Inverted leads for packaged isolation devices Sep 9, 2019 Issued
Array ( [id] => 15331919 [patent_doc_number] => 20200006289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => SEMICONDUCTOR PACKAGE STRUCTURE HAVING AN ANNULAR FRAME WITH TRUNCATED CORNERS [patent_app_type] => utility [patent_app_number] => 16/563919 [patent_app_country] => US [patent_app_date] => 2019-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16563919 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/563919
Semiconductor package structure having an annular frame with truncated corners Sep 7, 2019 Issued
Array ( [id] => 17424268 [patent_doc_number] => 11257729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Semiconductor device and method of forming encapsulated wafer level chip scale package (eWLCSP) [patent_app_type] => utility [patent_app_number] => 16/558135 [patent_app_country] => US [patent_app_date] => 2019-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 56 [patent_no_of_words] => 21648 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16558135 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/558135
Semiconductor device and method of forming encapsulated wafer level chip scale package (eWLCSP) Aug 31, 2019 Issued
Array ( [id] => 18919181 [patent_doc_number] => 11881470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Method for manufacturing mounting structure for electronic component, mounting structure for electronic component, electronic module, and wiring sheet [patent_app_type] => utility [patent_app_number] => 17/267887 [patent_app_country] => US [patent_app_date] => 2019-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 4172 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17267887 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/267887
Method for manufacturing mounting structure for electronic component, mounting structure for electronic component, electronic module, and wiring sheet Aug 29, 2019 Issued
Array ( [id] => 15260091 [patent_doc_number] => 20190378779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => MODULE [patent_app_type] => utility [patent_app_number] => 16/550454 [patent_app_country] => US [patent_app_date] => 2019-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550454 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/550454
Module equipped with a heat dissipation member Aug 25, 2019 Issued
Array ( [id] => 16660661 [patent_doc_number] => 20210057298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/547579 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547579 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/547579
Semiconductor package and method of forming the same Aug 21, 2019 Issued
Array ( [id] => 16959115 [patent_doc_number] => 11062998 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-13 [patent_title] => Semiconductor package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/547567 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547567 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/547567
Semiconductor package and manufacturing method thereof Aug 21, 2019 Issued
Array ( [id] => 17018424 [patent_doc_number] => 11088069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Semiconductor package and semiconductor device [patent_app_type] => utility [patent_app_number] => 16/547583 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5412 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547583 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/547583
Semiconductor package and semiconductor device Aug 21, 2019 Issued
Array ( [id] => 16973628 [patent_doc_number] => 11069608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/547602 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 48 [patent_no_of_words] => 20775 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547602 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/547602
Semiconductor structure and manufacturing method thereof Aug 21, 2019 Issued
Array ( [id] => 16660666 [patent_doc_number] => 20210057303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => SEMICONDUCTOR DIE, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/547599 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547599 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/547599
Semiconductor die, manufacturing method thereof, and semiconductor package Aug 21, 2019 Issued
Array ( [id] => 16660719 [patent_doc_number] => 20210057356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => SEMICONDUCTOR PACKAGE DEVICE AND SEMICONDUCTOR PROCESS [patent_app_type] => utility [patent_app_number] => 16/547539 [patent_app_country] => US [patent_app_date] => 2019-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8009 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547539 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/547539
Semiconductor package device and semiconductor process Aug 20, 2019 Issued
Array ( [id] => 16316157 [patent_doc_number] => 20200294895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-17 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/540119 [patent_app_country] => US [patent_app_date] => 2019-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16540119 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/540119
SEMICONDUCTOR DEVICE Aug 13, 2019 Abandoned
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