Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14691615 [patent_doc_number] => 20190244923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => METAL PAD MODIFICATION [patent_app_type] => utility [patent_app_number] => 16/390193 [patent_app_country] => US [patent_app_date] => 2019-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16390193 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/390193
Metal pad modification Apr 21, 2019 Issued
Array ( [id] => 14691605 [patent_doc_number] => 20190244918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => METHODS OF FORMING CONNECTOR PAD STRUCTURES, INTERCONNECT STRUCTURES, AND STRUCTURES THEREOF [patent_app_type] => utility [patent_app_number] => 16/390628 [patent_app_country] => US [patent_app_date] => 2019-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16390628 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/390628
Methods of forming connector pad structures, interconnect structures, and structures thereof Apr 21, 2019 Issued
Array ( [id] => 14722433 [patent_doc_number] => 20190252280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 16/390437 [patent_app_country] => US [patent_app_date] => 2019-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16390437 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/390437
Packaged semiconductor devices and methods of packaging semiconductor devices Apr 21, 2019 Issued
Array ( [id] => 14691567 [patent_doc_number] => 20190244899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => INCREASED CONTACT ALIGNMENT TOLERANCE FOR DIRECT BONDING [patent_app_type] => utility [patent_app_number] => 16/388692 [patent_app_country] => US [patent_app_date] => 2019-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16388692 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/388692
Increased contact alignment tolerance for direct bonding Apr 17, 2019 Issued
Array ( [id] => 16379342 [patent_doc_number] => 20200328185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => STRUCTURE AND FORMATION METHOD OF PACKAGE STRUCTURE WITH UNDERFILL [patent_app_type] => utility [patent_app_number] => 16/383929 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16383929 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/383929
Structure and formation method of package structure with underfill Apr 14, 2019 Issued
Array ( [id] => 16379334 [patent_doc_number] => 20200328177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => Mitigating Cracking Within Integrated Circuit (IC) Device Carrier [patent_app_type] => utility [patent_app_number] => 16/384148 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16384148 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/384148
Mitigating cracking within integrated circuit (IC) device carrier Apr 14, 2019 Issued
Array ( [id] => 16379308 [patent_doc_number] => 20200328151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => STRIPPED REDISTRUBUTION-LAYER FABRICATION FOR PACKAGE-TOP EMBEDDED MULTI-DIE INTERCONNECT BRIDGE [patent_app_type] => utility [patent_app_number] => 16/384348 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16384348 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/384348
Stripped redistrubution-layer fabrication for package-top embedded multi-die interconnect bridge Apr 14, 2019 Issued
Array ( [id] => 16553042 [patent_doc_number] => 10886207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/383746 [patent_app_country] => US [patent_app_date] => 2019-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 6080 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16383746 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/383746
Semiconductor device Apr 14, 2019 Issued
Array ( [id] => 16746456 [patent_doc_number] => 10971457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Semiconductor device comprising a composite material clip [patent_app_type] => utility [patent_app_number] => 16/382866 [patent_app_country] => US [patent_app_date] => 2019-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5681 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16382866 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/382866
Semiconductor device comprising a composite material clip Apr 11, 2019 Issued
Array ( [id] => 16819953 [patent_doc_number] => 11004791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Semiconductor chip with stacked conductor lines and air gaps [patent_app_type] => utility [patent_app_number] => 16/382774 [patent_app_country] => US [patent_app_date] => 2019-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 9191 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16382774 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/382774
Semiconductor chip with stacked conductor lines and air gaps Apr 11, 2019 Issued
Array ( [id] => 16356503 [patent_doc_number] => 10797021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Semiconductor packages having improved thermal discharge and electromagnetic shielding characteristics [patent_app_type] => utility [patent_app_number] => 16/382376 [patent_app_country] => US [patent_app_date] => 2019-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 18 [patent_no_of_words] => 9905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16382376 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/382376
Semiconductor packages having improved thermal discharge and electromagnetic shielding characteristics Apr 11, 2019 Issued
Array ( [id] => 17523120 [patent_doc_number] => 20220108969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => POWER SEMICONDUCTOR MODULE AND POWER CONVERSION APPARATUS [patent_app_type] => utility [patent_app_number] => 17/429633 [patent_app_country] => US [patent_app_date] => 2019-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17429633 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/429633
Power semiconductor module and power conversion apparatus Apr 8, 2019 Issued
Array ( [id] => 15823095 [patent_doc_number] => 10636743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Electronic component package and manufacturing method of the same [patent_app_type] => utility [patent_app_number] => 16/375302 [patent_app_country] => US [patent_app_date] => 2019-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7152 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16375302 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/375302
Electronic component package and manufacturing method of the same Apr 3, 2019 Issued
Array ( [id] => 14587877 [patent_doc_number] => 20190221547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => DIE ENCAPSULATION IN OXIDE BONDED WAFER STACK [patent_app_type] => utility [patent_app_number] => 16/363356 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363356 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/363356
Die encapsulation in oxide bonded wafer stack Mar 24, 2019 Issued
Array ( [id] => 18105157 [patent_doc_number] => 11545051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Microcontroller board for the learning and practice of coding [patent_app_type] => utility [patent_app_number] => 16/295005 [patent_app_country] => US [patent_app_date] => 2019-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3306 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16295005 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/295005
Microcontroller board for the learning and practice of coding Mar 6, 2019 Issued
Array ( [id] => 16516073 [patent_doc_number] => 20200395331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => Wire Bonding Structure [patent_app_type] => utility [patent_app_number] => 16/970911 [patent_app_country] => US [patent_app_date] => 2019-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16970911 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/970911
Wire bonding structure Feb 24, 2019 Issued
Array ( [id] => 17486064 [patent_doc_number] => 20220093568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => FILM IN SUBSTRATE FOR RELEASING Z STACK-UP CONSTRAINT [patent_app_type] => utility [patent_app_number] => 17/424839 [patent_app_country] => US [patent_app_date] => 2019-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17424839 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/424839
Film in substrate for releasing z stack-up constraint Feb 21, 2019 Issued
Array ( [id] => 14475827 [patent_doc_number] => 20190189561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD WITH MULTIPLE REDISTRIBUTION LAYER AND FINE LINE CAPABILITY [patent_app_type] => utility [patent_app_number] => 16/278972 [patent_app_country] => US [patent_app_date] => 2019-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -36 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16278972 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/278972
SEMICONDUCTOR DEVICE AND METHOD WITH MULTIPLE REDISTRIBUTION LAYER AND FINE LINE CAPABILITY Feb 18, 2019 Abandoned
Array ( [id] => 19123665 [patent_doc_number] => 11967660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Photovoltaic building element [patent_app_type] => utility [patent_app_number] => 16/967927 [patent_app_country] => US [patent_app_date] => 2019-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16967927 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/967927
Photovoltaic building element Feb 12, 2019 Issued
Array ( [id] => 16536612 [patent_doc_number] => 10879226 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Stacked dies and methods for forming bonded structures [patent_app_type] => utility [patent_app_number] => 16/270466 [patent_app_country] => US [patent_app_date] => 2019-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 60 [patent_no_of_words] => 13840 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16270466 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/270466
Stacked dies and methods for forming bonded structures Feb 6, 2019 Issued
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