Search

Jasmine Jhihan B. Clark

Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )

Most Active Art Unit
2815
Art Unit(s)
2815, 2899, 3621, 2816, 2503
Total Applications
3065
Issued Applications
2831
Pending Applications
98
Abandoned Applications
163

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19108630 [patent_doc_number] => 11961744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Substrate processing apparatus and substrate processing method [patent_app_type] => utility [patent_app_number] => 16/978221 [patent_app_country] => US [patent_app_date] => 2019-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9127 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16978221 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/978221
Substrate processing apparatus and substrate processing method Jan 31, 2019 Issued
Array ( [id] => 19261006 [patent_doc_number] => 12021072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Method of manufacturing of advanced three-dimensional semiconductor structures and structures produced therefrom [patent_app_type] => utility [patent_app_number] => 16/961183 [patent_app_country] => US [patent_app_date] => 2019-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5637 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16961183 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/961183
Method of manufacturing of advanced three-dimensional semiconductor structures and structures produced therefrom Jan 21, 2019 Issued
Array ( [id] => 15760463 [patent_doc_number] => 10622360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Method of manufacturing a semiconductor device [patent_app_type] => utility [patent_app_number] => 16/253291 [patent_app_country] => US [patent_app_date] => 2019-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7535 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16253291 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/253291
Method of manufacturing a semiconductor device Jan 21, 2019 Issued
Array ( [id] => 16194173 [patent_doc_number] => 20200235022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => Method and Apparatus for Reducing Noise on Integrated Circuit using Broken Die Seal [patent_app_type] => utility [patent_app_number] => 16/252396 [patent_app_country] => US [patent_app_date] => 2019-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4646 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16252396 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/252396
Method and apparatus for reducing noise on integrated circuit using broken die seal Jan 17, 2019 Issued
Array ( [id] => 16738963 [patent_doc_number] => 10964629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Siderail with mold compound relief [patent_app_type] => utility [patent_app_number] => 16/252092 [patent_app_country] => US [patent_app_date] => 2019-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16252092 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/252092
Siderail with mold compound relief Jan 17, 2019 Issued
Array ( [id] => 14676585 [patent_doc_number] => 20190237407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/251147 [patent_app_country] => US [patent_app_date] => 2019-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16251147 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/251147
Semiconductor package and method of manufacturing the same Jan 17, 2019 Issued
Array ( [id] => 15840723 [patent_doc_number] => 20200135644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => INTEGRATED CIRCUIT STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/251439 [patent_app_country] => US [patent_app_date] => 2019-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16251439 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/251439
Integrated circuit structure Jan 17, 2019 Issued
Array ( [id] => 16249457 [patent_doc_number] => 10748832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Heat sink for a semiconductor chip device [patent_app_type] => utility [patent_app_number] => 16/250271 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16250271 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/250271
Heat sink for a semiconductor chip device Jan 16, 2019 Issued
Array ( [id] => 16194169 [patent_doc_number] => 20200235018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => TEMPORARY INTERCONNECT FOR USE IN TESTING A SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/250683 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16250683 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/250683
Temporary interconnect for use in testing a semiconductor package Jan 16, 2019 Issued
Array ( [id] => 16194203 [patent_doc_number] => 20200235052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => HEXAGONALLY ARRANGED CONNECTION PATTERNS FOR HIGH-DENSITY DEVICE PACKAGING [patent_app_type] => utility [patent_app_number] => 16/250394 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16250394 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/250394
Hexagonally arranged connection patterns for high-density device packaging Jan 16, 2019 Issued
Array ( [id] => 14587713 [patent_doc_number] => 20190221465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => Method of Forming a Chip Arrangement, Chip Arrangement, Method of Forming a Chip Package, and Chip Package [patent_app_type] => utility [patent_app_number] => 16/249142 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9192 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249142 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249142
Method of forming a chip arrangement, chip arrangement, method of forming a chip package, and chip package Jan 15, 2019 Issued
Array ( [id] => 16180399 [patent_doc_number] => 20200227368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/249500 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6209 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249500 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249500
Semiconductor structure and manufacturing method thereof Jan 15, 2019 Issued
Array ( [id] => 16180431 [patent_doc_number] => 20200227400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => ASSEMBLING OF CHIPS BY STACKING WITH ROTATION [patent_app_type] => utility [patent_app_number] => 16/249639 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249639 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249639
Assembling of chips by stacking with rotation Jan 15, 2019 Issued
Array ( [id] => 16502576 [patent_doc_number] => 10867974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-15 [patent_title] => Semiconductor package and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 16/249446 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249446 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249446
Semiconductor package and method of fabricating the same Jan 15, 2019 Issued
Array ( [id] => 15598031 [patent_doc_number] => 20200075550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => MULTI-WAFER BONDING STRUCTURE AND BONDING METHOD [patent_app_type] => utility [patent_app_number] => 16/249118 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12341 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 389 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249118 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249118
Multi-wafer bonding structure and bonding method Jan 15, 2019 Issued
Array ( [id] => 15840531 [patent_doc_number] => 20200135548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/249440 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4992 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249440 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249440
Semiconductor device and method of forming the same Jan 15, 2019 Issued
Array ( [id] => 14587873 [patent_doc_number] => 20190221545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => MULTI-LAYER CHIP AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/249449 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249449 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249449
Multi-layer chip and fabrication method thereof Jan 15, 2019 Issued
Array ( [id] => 15351751 [patent_doc_number] => 20200013767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 16/248533 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5007 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16248533 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/248533
Semiconductor package Jan 14, 2019 Issued
Array ( [id] => 14753027 [patent_doc_number] => 20190259687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/247054 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16247054 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/247054
Semiconductor device Jan 13, 2019 Issued
Array ( [id] => 16180361 [patent_doc_number] => 20200227330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => SUBSTRATES FOR SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 16/245363 [patent_app_country] => US [patent_app_date] => 2019-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3191 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16245363 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/245363
Substrates for semiconductor packages Jan 10, 2019 Issued
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