
Jasmine Jhihan B. Clark
Examiner (ID: 17130, Phone: (571)272-1726 , Office: P/2816 )
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815, 2899, 3621, 2816, 2503 |
| Total Applications | 3065 |
| Issued Applications | 2831 |
| Pending Applications | 98 |
| Abandoned Applications | 163 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17801243
[patent_doc_number] => 11415536
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-16
[patent_title] => Gas sensor module and method of manufacturing gas sensor module
[patent_app_type] => utility
[patent_app_number] => 16/472134
[patent_app_country] => US
[patent_app_date] => 2017-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 42
[patent_no_of_words] => 10793
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16472134
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/472134 | Gas sensor module and method of manufacturing gas sensor module | Nov 5, 2017 | Issued |
Array
(
[id] => 14985127
[patent_doc_number] => 10446484
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-15
[patent_title] => Through-silicon via with improved substrate contact for reduced through-silicon via (TSV) capacitance variability
[patent_app_type] => utility
[patent_app_number] => 15/801501
[patent_app_country] => US
[patent_app_date] => 2017-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2406
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15801501
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/801501 | Through-silicon via with improved substrate contact for reduced through-silicon via (TSV) capacitance variability | Nov 1, 2017 | Issued |
Array
(
[id] => 12436641
[patent_doc_number] => 09978731
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-05-22
[patent_title] => Fan-out semiconductor package module
[patent_app_type] => utility
[patent_app_number] => 15/800951
[patent_app_country] => US
[patent_app_date] => 2017-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 22
[patent_no_of_words] => 12276
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15800951
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/800951 | Fan-out semiconductor package module | Oct 31, 2017 | Issued |
Array
(
[id] => 16516018
[patent_doc_number] => 20200395276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-17
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/630690
[patent_app_country] => US
[patent_app_date] => 2017-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7353
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 284
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16630690
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/630690 | Semiconductor device | Oct 25, 2017 | Issued |
Array
(
[id] => 12208560
[patent_doc_number] => 20180053785
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-22
[patent_title] => 'SYSTEM ON CHIP FULLY-DEPLETED SILICON ON INSULATOR WITH RF AND MM-WAVE INTEGRATED FUNCTIONS'
[patent_app_type] => utility
[patent_app_number] => 15/794257
[patent_app_country] => US
[patent_app_date] => 2017-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 4721
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15794257
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/794257 | System on chip fully-depleted silicon on insulator with RF and MM-wave integrated functions | Oct 25, 2017 | Issued |
Array
(
[id] => 12181638
[patent_doc_number] => 20180040573
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-08
[patent_title] => 'CHIP CARRIER AND METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 15/786623
[patent_app_country] => US
[patent_app_date] => 2017-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 21545
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15786623
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/786623 | Chip carrier and method thereof | Oct 17, 2017 | Issued |
Array
(
[id] => 12650298
[patent_doc_number] => 20180108597
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-19
[patent_title] => WIRE BONDING STRUCTURE AND ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/782487
[patent_app_country] => US
[patent_app_date] => 2017-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7439
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15782487
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/782487 | Wire bonding structure and electronic device | Oct 11, 2017 | Issued |
Array
(
[id] => 12162444
[patent_doc_number] => 20180033710
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-02-01
[patent_title] => 'ELECTRONIC DEVICE COMPRISING AN ENCAPSULATING BLOCK LOCALLY OF SMALLER THICKNESS'
[patent_app_type] => utility
[patent_app_number] => 15/728969
[patent_app_country] => US
[patent_app_date] => 2017-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2797
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728969
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/728969 | Electronic device comprising an encapsulating block locally of smaller thickness | Oct 9, 2017 | Issued |
Array
(
[id] => 13950705
[patent_doc_number] => 10211131
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-02-19
[patent_title] => Systems and methods for improved adhesion between a leadframe and molding compound in a semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/727048
[patent_app_country] => US
[patent_app_date] => 2017-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 4904
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15727048
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/727048 | Systems and methods for improved adhesion between a leadframe and molding compound in a semiconductor device | Oct 5, 2017 | Issued |
Array
(
[id] => 13006019
[patent_doc_number] => 10026680
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-17
[patent_title] => Semiconductor package and fabrication method thereof
[patent_app_type] => utility
[patent_app_number] => 15/725723
[patent_app_country] => US
[patent_app_date] => 2017-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 16
[patent_no_of_words] => 2432
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15725723
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/725723 | Semiconductor package and fabrication method thereof | Oct 4, 2017 | Issued |
Array
(
[id] => 12154742
[patent_doc_number] => 20180026006
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-25
[patent_title] => 'SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR ELEMENTS'
[patent_app_type] => utility
[patent_app_number] => 15/722747
[patent_app_country] => US
[patent_app_date] => 2017-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 11313
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15722747
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/722747 | Systems and methods for bonding semiconductor elements | Oct 1, 2017 | Issued |
Array
(
[id] => 17152541
[patent_doc_number] => 11145632
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-12
[patent_title] => High density die package configuration on system boards
[patent_app_type] => utility
[patent_app_number] => 16/636616
[patent_app_country] => US
[patent_app_date] => 2017-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 16
[patent_no_of_words] => 6420
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16636616
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/636616 | High density die package configuration on system boards | Sep 28, 2017 | Issued |
Array
(
[id] => 17516887
[patent_doc_number] => 11296048
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-04-05
[patent_title] => Semiconductor chip mounting device and method for manufacturing semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/338700
[patent_app_country] => US
[patent_app_date] => 2017-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 7705
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16338700
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/338700 | Semiconductor chip mounting device and method for manufacturing semiconductor device | Sep 28, 2017 | Issued |
Array
(
[id] => 12615288
[patent_doc_number] => 20180096926
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-04-05
[patent_title] => INTERCONNECTION SUBSTRATE AND SEMICONDUCTOR PACKAGE
[patent_app_type] => utility
[patent_app_number] => 15/718414
[patent_app_country] => US
[patent_app_date] => 2017-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6531
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15718414
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/718414 | Interconnection substrate and semiconductor package | Sep 27, 2017 | Issued |
Array
(
[id] => 12596442
[patent_doc_number] => 20180090644
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-29
[patent_title] => LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/717183
[patent_app_country] => US
[patent_app_date] => 2017-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6780
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15717183
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/717183 | Light emitting device and method for manufacturing thereof | Sep 26, 2017 | Issued |
Array
(
[id] => 17410260
[patent_doc_number] => 11251158
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-15
[patent_title] => Monolithic chip stacking using a die with double-sided interconnect layers
[patent_app_type] => utility
[patent_app_number] => 16/633543
[patent_app_country] => US
[patent_app_date] => 2017-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 7240
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16633543
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/633543 | Monolithic chip stacking using a die with double-sided interconnect layers | Sep 24, 2017 | Issued |
Array
(
[id] => 17410214
[patent_doc_number] => 11251111
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-15
[patent_title] => Leadframe in packages of integrated circuits
[patent_app_type] => utility
[patent_app_number] => 16/637556
[patent_app_country] => US
[patent_app_date] => 2017-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6495
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16637556
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/637556 | Leadframe in packages of integrated circuits | Sep 19, 2017 | Issued |
Array
(
[id] => 12122402
[patent_doc_number] => 20180005987
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-04
[patent_title] => 'SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 15/707646
[patent_app_country] => US
[patent_app_date] => 2017-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 22771
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15707646
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/707646 | Semiconductor package and fabricating method thereof | Sep 17, 2017 | Issued |
Array
(
[id] => 15611353
[patent_doc_number] => 10586746
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-10
[patent_title] => Semiconductor device and method
[patent_app_type] => utility
[patent_app_number] => 15/705567
[patent_app_country] => US
[patent_app_date] => 2017-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 63
[patent_no_of_words] => 12401
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15705567
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/705567 | Semiconductor device and method | Sep 14, 2017 | Issued |
Array
(
[id] => 15611353
[patent_doc_number] => 10586746
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-10
[patent_title] => Semiconductor device and method
[patent_app_type] => utility
[patent_app_number] => 15/705567
[patent_app_country] => US
[patent_app_date] => 2017-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 63
[patent_no_of_words] => 12401
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15705567
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/705567 | Semiconductor device and method | Sep 14, 2017 | Issued |