Jasmine Jhihan B. Clark

Array ( [id] => 13121685 [patent_doc_number] => 10079198 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-18 [patent_title] => QFN pre-molded leadframe having a solder wettable sidewall on each lead [patent_app_type] => utility [patent_app_number] => 15/610088 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4470 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15610088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16781730 [patent_doc_number] => 20210118809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => MICROELECTRONIC PACKAGE HAVING ELECTROMAGNETIC INTERFERENCE SHIELDING [patent_app_type] => utility [patent_app_number] => 16/606628 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16606628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13031075 [patent_doc_number] => 10038164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Method of manufacturing a display device and a display device [patent_app_type] => utility [patent_app_number] => 15/606897 [patent_app_country] => US [patent_app_date] => 2017-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6899 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15606897 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12436464 [patent_doc_number] => 09978672 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-22 [patent_title] => Transistor package with terminals coupled via chip carrier [patent_app_type] => utility [patent_app_number] => 15/603476 [patent_app_country] => US [patent_app_date] => 2017-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7893 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15603476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13769435 [patent_doc_number] => 10177067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Manufacturing method of package carrier [patent_app_type] => utility [patent_app_number] => 15/598324 [patent_app_country] => US [patent_app_date] => 2017-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 5160 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15598324 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14011713 [patent_doc_number] => 10224332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Memory device having vertical structure [patent_app_type] => utility [patent_app_number] => 15/598570 [patent_app_country] => US [patent_app_date] => 2017-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7509 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15598570 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13573653 [patent_doc_number] => 20180338375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => LOW CROSSTALK VERTICAL CONNECTION INTERFACE [patent_app_type] => utility [patent_app_number] => 15/597505 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15597505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14491893 [patent_doc_number] => 10332745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Dummy assist features for pattern support [patent_app_type] => utility [patent_app_number] => 15/597277 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3001 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15597277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12314601 [patent_doc_number] => 09941253 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-10 [patent_title] => Semiconductor packages including interconnectors and methods of fabricating the same [patent_app_type] => utility [patent_app_number] => 15/597484 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6078 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15597484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14094107 [patent_doc_number] => 10242967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-26 [patent_title] => Die encapsulation in oxide bonded wafer stack [patent_app_type] => utility [patent_app_number] => 15/596663 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 5739 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13571135 [patent_doc_number] => 20180337115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => INTEGRATED SHUNT IN CIRCUIT PACKAGE [patent_app_type] => utility [patent_app_number] => 15/596550 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13571165 [patent_doc_number] => 20180337130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/596956 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596956 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12759577 [patent_doc_number] => 20180145027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => METHOD FOR FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTERCONNECTION PART OF AN INTEGRATED CIRCUIT WITHOUT ADDITION OF ADDITIONAL MATERIAL, AND CORRESPONDING INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/596877 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12095510 [patent_doc_number] => 20170352603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'ELECTRONIC COMPONENT PACKAGE INCLUDING SEALING RESIN LAYER, METAL MEMBER, CERAMIC SUBSTRATE, AND ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/597115 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11099 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15597115 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12759613 [patent_doc_number] => 20180145039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => METHOD FOR FORMING AT LEAST ONE ELECTRICAL DISCONTINUITY IN AN INTERCONNECTION PART OF AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 15/596772 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596772 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14382021 [patent_doc_number] => 20190164923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => SUBSTRATE DEVICE, ELECTRONIC APPARATUS, AND METHOD FOR MANUFACTURING SUBSTRATE DEVICE [patent_app_type] => utility [patent_app_number] => 16/307091 [patent_app_country] => US [patent_app_date] => 2017-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16307091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11967155 [patent_doc_number] => 20170271307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/594313 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 34353 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15594313 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15775799 [patent_doc_number] => 20200118917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => DIELECTRIC FOR HIGH DENSITY SUBSTRATE INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 16/603863 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16603863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14011573 [patent_doc_number] => 10224262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Flexible heat spreader lid [patent_app_type] => utility [patent_app_number] => 15/593969 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15593969 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12061803 [patent_doc_number] => 20170338146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'Method for Patterning Interconnects' [patent_app_type] => utility [patent_app_number] => 15/593149 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 19146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15593149 [rel_patent_id] =>[rel_patent_doc_number] =>)