Jasmine Jhihan B. Clark

Array ( [id] => 11904299 [patent_doc_number] => 09773739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Mark structure and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 15/397788 [patent_app_country] => US [patent_app_date] => 2017-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 8555 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15397788 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14671937 [patent_doc_number] => 10373888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Electronic package assembly with compact die placement [patent_app_type] => utility [patent_app_number] => 15/395985 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 7261 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11710404 [patent_doc_number] => 20170178903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'Single Crystal Rhombohedral Epitaxy of SiGe on Sapphire at 450°C - 500°C Substrate Temperatures' [patent_app_type] => utility [patent_app_number] => 15/386592 [patent_app_country] => US [patent_app_date] => 2016-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15386592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12849466 [patent_doc_number] => 20180174995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => BONDED STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/387385 [patent_app_country] => US [patent_app_date] => 2016-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15387385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11725510 [patent_doc_number] => 09698377 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-04 [patent_title] => 'Copolymer and resin composition, packaging film and package structure including the same' [patent_app_type] => utility [patent_app_number] => 15/386400 [patent_app_country] => US [patent_app_date] => 2016-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 5036 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15386400 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14459765 [patent_doc_number] => 10325856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Electronic component package and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/385414 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 7107 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15385414 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11673770 [patent_doc_number] => 20170162494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'METHOD FOR FABRICATING PACKAGE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/383362 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4419 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15383362 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13159469 [patent_doc_number] => 10096468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Method of improving adhesion [patent_app_type] => utility [patent_app_number] => 15/383162 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3059 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15383162 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12416961 [patent_doc_number] => 09972603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Seal-ring structure for stacking integrated circuits [patent_app_type] => utility [patent_app_number] => 15/383419 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 34 [patent_no_of_words] => 10144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15383419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11710530 [patent_doc_number] => 20170179029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'INCREASED CONTACT ALIGNMENT TOLERANCE FOR DIRECT BONDING' [patent_app_type] => utility [patent_app_number] => 15/379942 [patent_app_country] => US [patent_app_date] => 2016-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15379942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11911190 [patent_doc_number] => 09780010 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-03 [patent_title] => 'Hermetic package with improved RF stability and performance' [patent_app_type] => utility [patent_app_number] => 15/378575 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4577 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15378575 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12256863 [patent_doc_number] => 09929012 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-27 [patent_title] => 'Resist having tuned interface hardmask layer for EUV exposure' [patent_app_type] => utility [patent_app_number] => 15/378655 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4500 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15378655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11710514 [patent_doc_number] => 20170179013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'WIRING BOARD, AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/376854 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11319 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15376854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13640659 [patent_doc_number] => 09847290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-19 [patent_title] => Through-silicon via with improved substrate contact for reduced through-silicon via (TSV) capacitance variability [patent_app_type] => utility [patent_app_number] => 15/375924 [patent_app_country] => US [patent_app_date] => 2016-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2406 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15375924 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13111919 [patent_doc_number] => 10074617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-11 [patent_title] => Wafer level package (WLP) and method for forming the same [patent_app_type] => utility [patent_app_number] => 15/376437 [patent_app_country] => US [patent_app_date] => 2016-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 5463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15376437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12174841 [patent_doc_number] => 09892989 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-13 [patent_title] => 'Wafer-level chip scale package with side protection' [patent_app_type] => utility [patent_app_number] => 15/373393 [patent_app_country] => US [patent_app_date] => 2016-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 4413 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15373393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11690724 [patent_doc_number] => 20170166440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'MICROELECTROMECHANICAL DEVICE AND METHOD FOR MANUFACTURING IT' [patent_app_type] => utility [patent_app_number] => 15/372660 [patent_app_country] => US [patent_app_date] => 2016-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6323 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15372660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12229822 [patent_doc_number] => 09917071 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-13 [patent_title] => 'Semiconductor packages' [patent_app_type] => utility [patent_app_number] => 15/371889 [patent_app_country] => US [patent_app_date] => 2016-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4136 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15371889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11557688 [patent_doc_number] => 20170103934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'HEAT SINK FOR A SEMICONDUCTOR CHIP DEVICE' [patent_app_type] => utility [patent_app_number] => 15/370307 [patent_app_country] => US [patent_app_date] => 2016-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2454 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15370307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11817941 [patent_doc_number] => 09721900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'Semiconductor package and its manufacturing method' [patent_app_type] => utility [patent_app_number] => 15/364851 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 5709 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364851 [rel_patent_id] =>[rel_patent_doc_number] =>)